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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ff58f29cd5sm57420725ad.56.2024.08.04.21.33.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Aug 2024 21:33:49 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: dbarboza@ventanamicro.com, Palmer Dabbelt , Weiwei Li , zhiwei_liu@linux.alibaba.com, Alistair Francis , atishp@rivosinc.com, bmeng.cn@gmail.com, qemu-riscv@nongnu.org, alistair23@gmail.com Subject: [PATCH 1/2] include: bitops: Add mask extract64/deposit64 Date: Mon, 5 Aug 2024 14:33:35 +1000 Message-ID: <20240805043336.72548-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240805043336.72548-1-alistair.francis@wdc.com> References: <20240805043336.72548-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on the RISC-V get_field() and set_field() macros add mask_extract64() and mask_deposit64() bitop functions. These can extrac and deposit values into fields using a bit field mask directly instead of a length and shift. Signed-off-by: Alistair Francis --- include/qemu/bitops.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 2c0a2fe751..dd26f4a6b5 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -409,6 +409,22 @@ static inline uint64_t extract64(uint64_t value, int start, int length) return (value >> start) & (~0ULL >> (64 - length)); } +/** + * mask_extract64: + * @value: the value to extract the bit field from + * @mask: the mask bit field to extract + * + * Extract from the 64 bit input @value the bit mask specified by the + * @mask parameter, and return it. The value returned is shifted + * so that only the bit field is returned. + * + * Returns: the value of the bit field extracted from the input value. + */ +static inline uint64_t mask_extract64(uint64_t value, uint64_t mask) +{ + return (value & mask) / (mask & ~(mask << 1)); +} + /** * sextract32: * @value: the value to extract the bit field from @@ -511,6 +527,25 @@ static inline uint64_t deposit64(uint64_t value, int start, int length, return (value & ~mask) | ((fieldval << start) & mask); } +/** + * mask_deposit64: + * @value: initial value to insert bit field into + * @mask: the mask bit field + * @fieldval: the value to insert into the bit field + * + * Deposit @fieldval into the 64 bit @value at the bit field specified + * by the @mask parameter, and return the modified + * @value. Bits of @value outside the bit field are not modified. + * Bits of @fieldval above @mask bits are ignored. + * + * Returns: the modified @value. + */ +static inline uint64_t mask_deposit64(uint64_t value, uint64_t mask, + uint64_t fieldval) +{ + return (value & ~mask) | ((fieldval * (mask & ~(mask << 1))) & mask); +} + /** * half_shuffle32: * @x: 32-bit value (of which only the bottom 16 bits are of interest)