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Mon, 05 Aug 2024 13:17:45 -0700 (PDT) Date: Mon, 5 Aug 2024 13:17:09 -0700 In-Reply-To: <20240805201719.2345596-1-tavip@google.com> Mime-Version: 1.0 References: <20240805201719.2345596-1-tavip@google.com> X-Mailer: git-send-email 2.46.0.rc2.264.g509ed76dc8-goog Message-ID: <20240805201719.2345596-15-tavip@google.com> Subject: [RFC PATCH 14/23] test/unit: add unit tests for flexcomm i2c From: Octavian Purdila To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, stefanst@google.com, pbonzini@redhat.com, alex.bennee@linaro.org, thuth@redhat.com, peter.maydell@linaro.org, marcandre.lureau@redhat.com, alistair@alistair23.me, berrange@redhat.com, philmd@linaro.org, jsnow@redhat.com, crosa@redhat.com, bleal@redhat.com Received-SPF: pass client-ip=2607:f8b0:4864:20::b49; envelope-from=3aTOxZgUKCtAFwH4B2AA270.yA8C08G-z0H079A929G.AD2@flex--tavip.bounces.google.com; helo=mail-yb1-xb49.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add master mode tests for flexcomm i2c. Signed-off-by: Octavian Purdila --- tests/unit/meson.build | 10 ++ tests/unit/test-flexcomm-i2c.c | 209 +++++++++++++++++++++++++++++++++ 2 files changed, 219 insertions(+) create mode 100644 tests/unit/test-flexcomm-i2c.c diff --git a/tests/unit/meson.build b/tests/unit/meson.build index 4c22cb3ccc..3491e2003b 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -160,6 +160,16 @@ if have_system meson.project_source_root() / 'hw/i2c/flexcomm_i2c.c', meson.project_source_root() / 'hw/i2c/core.c', ], + 'test-flexcomm-i2c': [ + hwcore, chardev, qom, migration, + meson.project_source_root() / 'hw/core/gpio.c', + meson.project_source_root() / 'tests/unit/sysbus-mock.c', + meson.project_source_root() / 'hw/misc/flexcomm.c', + meson.project_source_root() / 'hw/char/flexcomm_usart.c', + meson.project_source_root() / 'hw/i2c/flexcomm_i2c.c', + meson.project_source_root() / 'hw/i2c/core.c', + 'i2c_tester.c', + ], } if config_host_data.get('CONFIG_INOTIFY1') tests += {'test-util-filemonitor': []} diff --git a/tests/unit/test-flexcomm-i2c.c b/tests/unit/test-flexcomm-i2c.c new file mode 100644 index 0000000000..9d02c94101 --- /dev/null +++ b/tests/unit/test-flexcomm-i2c.c @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2024 Google LLC. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +#include "qemu/config-file.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "qemu/sockets.h" +#include "sysemu/sysemu.h" +#include "qemu/main-loop.h" +#include "qemu/option.h" +#include "exec/memory.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-core.h" + +#include "hw/i2c/flexcomm_i2c.h" +#include "i2c_tester.h" +#include "sysbus-mock.h" +#include "reg-utils.h" + +#define PERIPH_ADDR (0x20) +#define INVALID_ADDR (0x10) + +#define REG_ADDR 0x11 +#define REG_VALUE 0xAA + +#define FLEXCOMM_BASE 0x40106000UL +#define FLEXCOMM_I2C_BASE FLEXCOMM_BASE + +typedef struct { + DeviceState *dev; + I2CSlave *periph; + bool irq; +} TestFixture; + +/* Callback for the interrupt line. */ +static void spi_irq_set(void *opaque, int line, int level) +{ + TestFixture *f = (TestFixture *)opaque; + + f->irq = level; +} + +/* + * Test fixture initialization. + */ +static void set_up(TestFixture *f, gconstpointer data) +{ + FlexcommState *s; + + f->dev = qdev_new(TYPE_FLEXCOMM); + g_assert(f->dev); + + s = FLEXCOMM(f->dev); + s->irq = qemu_allocate_irq(spi_irq_set, f, 0); + + if (data != NULL) { + qdev_prop_set_int32(DEVICE(f->dev), "functions", (uintptr_t)data); + } + + qdev_realize_and_unref(f->dev, NULL, &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(f->dev), 0, FLEXCOMM_BASE); + + device_cold_reset(f->dev); + + f->periph = i2c_slave_create_simple(s->i2c, TYPE_I2C_TESTER, PERIPH_ADDR); +} + +static void tear_down(TestFixture *f, gconstpointer user_data) +{ + qdev_unrealize(f->dev); + qdev_unrealize(DEVICE(f->periph)); +} + +static void master_test(TestFixture *f, gconstpointer user_data) +{ + uint32_t tmp; + + /* Select and lock I2C */ + tmp = FLEXCOMM_PSELID_LOCK_Msk | FLEXCOMM_PERSEL_I2C; + REG32_WRITE(f->dev, FLEXCOMM, PSELID, tmp); + + /* Enable master mode */ + REG32_WRITE_FIELD(f->dev, FLEXCOMM_I2C, CFG, MSTEN, 1); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, CFG, MSTEN) == 1); + + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTPENDING) == 1); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_IDLE); + + /* Enable interrupts */ + REG32_WRITE_FIELD(f->dev, FLEXCOMM_I2C, INTENSET, MSTPENDINGEN, 1); + g_assert(f->irq == true); + + /* start for invalid address */ + REG32_WRITE(f->dev, FLEXCOMM_I2C, MSTDAT, INVALID_ADDR); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTSTART, 1); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_NAKADR); + g_assert(f->irq == true); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTSTOP, 1); + + /* write past the last register */ + REG32_WRITE_FIELD(f->dev, FLEXCOMM_I2C, MSTDAT, DATA, PERIPH_ADDR); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTSTART, 1); + g_assert(f->irq == true); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_TXRDY); + REG32_WRITE_FIELD(f->dev, FLEXCOMM_I2C, MSTDAT, DATA, + (I2C_TESTER_NUM_REGS + 10)); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTCONTINUE, 1); + g_assert(f->irq == true); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_TXRDY); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTCONTINUE, 1); + g_assert(f->irq == true); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_NAKDAT); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTSTOP, 1); + + /* write value to register */ + REG32_WRITE_FIELD(f->dev, FLEXCOMM_I2C, MSTDAT, DATA, PERIPH_ADDR); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTSTART, 1); + g_assert(f->irq == true); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_TXRDY); + REG32_WRITE_FIELD(f->dev, FLEXCOMM_I2C, MSTDAT, DATA, REG_ADDR); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTCONTINUE, 1); + g_assert(f->irq == true); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_TXRDY); + REG32_WRITE_FIELD(f->dev, FLEXCOMM_I2C, MSTDAT, DATA, REG_VALUE); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTCONTINUE, 1); + g_assert(f->irq == true); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_TXRDY); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTSTOP, 1); + g_assert(f->irq == true); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_IDLE); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTSTOP, 1); + + /* read value back from register */ + REG32_WRITE_FIELD(f->dev, FLEXCOMM_I2C, MSTDAT, DATA, PERIPH_ADDR); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTSTART, 1); + g_assert(f->irq == true); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_TXRDY); + REG32_WRITE_FIELD(f->dev, FLEXCOMM_I2C, MSTDAT, DATA, REG_ADDR); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTCONTINUE, 1); + g_assert(f->irq == true); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_TXRDY); + REG32_WRITE_FIELD(f->dev, FLEXCOMM_I2C, MSTDAT, DATA, (PERIPH_ADDR + 1)); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTSTART, 1); + g_assert(f->irq == true); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_RXRDY); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTCONTINUE, 1); + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, MSTDAT, DATA) == REG_VALUE); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTSTOP, 1); + + /* + * Check that the master ended the transaction (i.e. i2c_end_transfer was + * called). If the master does not properly end the transaction this would + * be seen as a restart and it would not be NACKed. + */ + REG32_WRITE_FIELD(f->dev, FLEXCOMM_I2C, MSTDAT, DATA, INVALID_ADDR); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTSTART, 1); + + g_assert(REG32_READ_FIELD(f->dev, FLEXCOMM_I2C, STAT, MSTSTATE) == + MSTSTATE_NAKADR); + g_assert(f->irq == true); + REG32_WRITE_FIELD_NOUPDATE(f->dev, FLEXCOMM_I2C, MSTCTL, MSTSTOP, 1); + + /* Disable interrupts */ + REG32_WRITE_FIELD(f->dev, FLEXCOMM_I2C, INTENCLR, MSTPENDINGCLR, 1); + g_assert(f->irq == false); +} + +/* mock-up */ +const PropertyInfo qdev_prop_chr; + +int main(int argc, char **argv) +{ + qemu_init_main_loop(&error_abort); + + g_test_init(&argc, &argv, NULL); + + /* Initialize object types. */ + sysbus_mock_init(); + module_call_init(MODULE_INIT_QOM); + qemu_add_opts(&qemu_chardev_opts); + + g_test_add("/flexcomm-i2c/master", TestFixture, + (gconstpointer)(1 << FLEXCOMM_FUNC_I2C), + set_up, master_test, tear_down); + + return g_test_run(); +}