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Mon, 05 Aug 2024 13:17:29 -0700 (PDT) Date: Mon, 5 Aug 2024 13:17:00 -0700 In-Reply-To: <20240805201719.2345596-1-tavip@google.com> Mime-Version: 1.0 References: <20240805201719.2345596-1-tavip@google.com> X-Mailer: git-send-email 2.46.0.rc2.264.g509ed76dc8-goog Message-ID: <20240805201719.2345596-6-tavip@google.com> Subject: [RFC PATCH 05/23] hw: add register access utility functions From: Octavian Purdila To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, stefanst@google.com, pbonzini@redhat.com, alex.bennee@linaro.org, thuth@redhat.com, peter.maydell@linaro.org, marcandre.lureau@redhat.com, alistair@alistair23.me, berrange@redhat.com, philmd@linaro.org, jsnow@redhat.com, crosa@redhat.com, bleal@redhat.com Received-SPF: pass client-ip=2607:f8b0:4864:20::54a; envelope-from=3WTOxZgUKCsAzg1ovmuumrk.iuswks0-jk1krtutmt0.uxm@flex--tavip.bounces.google.com; helo=mail-pg1-x54a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add register access utility functions for device models, like checking aligned access and reading and writing to a register backstore. Signed-off-by: Octavian Purdila --- include/hw/regs.h | 89 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 include/hw/regs.h diff --git a/include/hw/regs.h b/include/hw/regs.h new file mode 100644 index 0000000000..8d0da0629d --- /dev/null +++ b/include/hw/regs.h @@ -0,0 +1,89 @@ +/* + * Useful macros/functions for register handling. + * + * Copyright (c) 2021 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef HW_REGS_H +#define HW_REGS_H + +#include "exec/hwaddr.h" +#include "exec/memattrs.h" + +#define BITS(hi, lo) (BIT(hi + 1) - BIT(lo)) +#define BIT_IS_SET(v, b) (((v) & BIT(b)) != 0) + +/* + * reg32_aligned_access + * @addr: address to check + * @size: size of access + * + * Check if access to a hardware address is 32bit aligned. + * + * Returns: true if access is 32bit aligned, false otherwise + */ +static inline bool reg32_aligned_access(hwaddr addr, unsigned size) +{ + if (size != 4 || addr % 4 != 0) { + return false; + } + return true; +} + +/* + * reg32_write + * @base: base address + * @addr: register offset in bytes + * @val: value to write + * @wr_bits_array: RW bitmask array + * + * Update the RW/WO bits of a 32bit register backstore with a given value + * (discarding updats to the RO bits). The RW/WO bits are encoded in the + * @wr_bits_array with bits set being RW and bits unset being RO. + * + * Usage example: + * + * wr_bits_array[] = { + * [REG1_ADDR/4] = 0xFF000000, // MSB byte writable + * [REG2_ADDR/4] = 0xFF, // LSB byte writable + * // all other registers are read-only + * }; + * + * // backstore is updated to 0x12000000 + * reg32_write(&backstore, REG1_ADDR, 0x12345678, wr_bits_array); + * // backstore is updated to 0x78 + * reg32_write(&backstore, REG2_ADDR, 0x12345678, wr_bits_array); + */ +static inline uint32_t reg32_write(void *base, uint32_t off, uint32_t val, + const uint32_t *rw_bits_array) +{ + uint32_t *ptr = base + addr; + uint32_t old_value = *ptr; + uint32_t mask = rw_bits_array ? rw_bits_array[addr / 4] : 0xFFFFFFFF; + + /* set WO/RW bits */ + *ptr |= val & mask; + /* clear RO bits */ + *ptr &= val | ~mask; + + return old_value; +} + +/* + * reg32_read + * @base: base address + * @addr: register offset in bytes + * + * Returns: 32bit value from register backstore + */ +static inline uint32_t reg32_read(void *base, uint32_t addr) +{ + return *(uint32_t *)(base + addr); +} + +#endif /* HW_REGS_H */