| Message ID | 20240807000652.1417776-14-debug@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv support for control flow integrity extensions | expand |
On 8/7/24 10:06, Deepak Gupta wrote: > sspush/sspopchk have compressed encodings carved out of zcmops. > compressed sspush is designated as c.mop.1 while compressed sspopchk > is designated as c.mop.5. > > Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly > c.sspopchk x5 exists while c.sspopchk x1 doesn't. > > Signed-off-by: Deepak Gupta <debug@rivosinc.com> > Co-developed-by: Jim Shu <jim.shu@sifive.com> > Co-developed-by: Andy Chiu <andy.chiu@sifive.com> > --- > target/riscv/insn16.decode | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode > index 3953bcf82d..d9fb74fef6 100644 > --- a/target/riscv/insn16.decode > +++ b/target/riscv/insn16.decode > @@ -69,10 +69,12 @@ > # Formats 16: > @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd > @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd > +@c_sspop ... . ..... ..... .. &i imm=0 rs1=5 rd=0 > @cl_q ... . ..... ..... .. &i imm=%uimm_cl_q rs1=%rs1_3 rd=%rs2_3 > @cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 > @cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 > @cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3 > +@c_sspush ... ... ... .. ... .. &s imm=0 rs1=0 rs2=1 > @cs_q ... ... ... .. ... .. &s imm=%uimm_cl_q rs1=%rs1_3 rs2=%rs2_3 > @cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 > @cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 > @@ -140,6 +142,8 @@ sw 110 ... ... .. ... 00 @cs_w > addi 000 . ..... ..... 01 @ci > addi 010 . ..... ..... 01 @c_li > { > + sspush 011 0 00001 00000 01 @c_sspush # c.sspush x1 carving out of zcmops > + sspopchk 011 0 00101 00000 01 @c_sspop # c.sspopchk x5 carving out of zcmops Again, drop the single-use formats. r~
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 3953bcf82d..d9fb74fef6 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -69,10 +69,12 @@ # Formats 16: @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd +@c_sspop ... . ..... ..... .. &i imm=0 rs1=5 rd=0 @cl_q ... . ..... ..... .. &i imm=%uimm_cl_q rs1=%rs1_3 rd=%rs2_3 @cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 @cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 @cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3 +@c_sspush ... ... ... .. ... .. &s imm=0 rs1=0 rs2=1 @cs_q ... ... ... .. ... .. &s imm=%uimm_cl_q rs1=%rs1_3 rs2=%rs2_3 @cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 @cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 @@ -140,6 +142,8 @@ sw 110 ... ... .. ... 00 @cs_w addi 000 . ..... ..... 01 @ci addi 010 . ..... ..... 01 @c_li { + sspush 011 0 00001 00000 01 @c_sspush # c.sspush x1 carving out of zcmops + sspopchk 011 0 00101 00000 01 @c_sspop # c.sspopchk x5 carving out of zcmops c_mop_n 011 0 0 n:3 1 00000 01 illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0 addi 011 . 00010 ..... 01 @c_addi16sp
sspush/sspopchk have compressed encodings carved out of zcmops. compressed sspush is designated as c.mop.1 while compressed sspopchk is designated as c.mop.5. Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly c.sspopchk x5 exists while c.sspopchk x1 doesn't. Signed-off-by: Deepak Gupta <debug@rivosinc.com> Co-developed-by: Jim Shu <jim.shu@sifive.com> Co-developed-by: Andy Chiu <andy.chiu@sifive.com> --- target/riscv/insn16.decode | 4 ++++ 1 file changed, 4 insertions(+)