| Message ID | 20240807000652.1417776-6-debug@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv support for control flow integrity extensions | expand |
On 8/7/24 10:06, Deepak Gupta wrote: > sw check exception support was recently added. This patch further augments > sw check exception by providing support for additional code which is > provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever > sw check exception is raised *tval gets the value deposited in > `sw_check_code`. > > Signed-off-by: Deepak Gupta <debug@rivosinc.com> > --- > target/riscv/cpu.h | 2 ++ > target/riscv/cpu_helper.c | 2 ++ > target/riscv/csr.c | 1 + > 3 files changed, 5 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 8c7841fc08..12334f9540 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -224,6 +224,8 @@ struct CPUArchState { > > /* elp state for zicfilp extension */ > cfi_elp elp; > + /* sw check code for sw check exception */ > + target_ulong sw_check_code; There's probably room for consolidating the different fields that feed into tval, to be set when raising the exception. But anyway, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8c7841fc08..12334f9540 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -224,6 +224,8 @@ struct CPUArchState { /* elp state for zicfilp extension */ cfi_elp elp; + /* sw check code for sw check exception */ + target_ulong sw_check_code; #ifdef CONFIG_USER_ONLY uint32_t elf_flags; bool ufcfien; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8c69c55576..364f3ee212 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1762,6 +1762,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) cs->watchpoint_hit = NULL; } break; + case RISCV_EXCP_SW_CHECK: + tval = env->sw_check_code; default: break; } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5771a14848..a5a969a377 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1179,6 +1179,7 @@ static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ + (1ULL << (RISCV_EXCP_SW_CHECK)) | \ (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
sw check exception support was recently added. This patch further augments sw check exception by providing support for additional code which is provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever sw check exception is raised *tval gets the value deposited in `sw_check_code`. Signed-off-by: Deepak Gupta <debug@rivosinc.com> --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 2 ++ target/riscv/csr.c | 1 + 3 files changed, 5 insertions(+)