From patchwork Thu Aug 8 02:49:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jamin Lin X-Patchwork-Id: 13756906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E48BC52D6F for ; Thu, 8 Aug 2024 02:51:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sbtDr-00080k-C8; Wed, 07 Aug 2024 22:49:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbtDp-0007tJ-HY; Wed, 07 Aug 2024 22:49:49 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sbtDo-0008AE-3J; Wed, 07 Aug 2024 22:49:49 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 8 Aug 2024 10:49:18 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 8 Aug 2024 10:49:18 +0800 To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Cleber Rosa , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Wainer dos Santos Moschetta" , Beraldo Leal , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v2 08/11] aspeed/soc: introduce a new API to get the INTC orgate information Date: Thu, 8 Aug 2024 10:49:13 +0800 Message-ID: <20240808024916.1262715-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240808024916.1262715-1-jamin_lin@aspeedtech.com> References: <20240808024916.1262715-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin X-Patchwork-Original-From: Jamin Lin via From: Jamin Lin Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently, users can set the intc mapping table with enumerated device id and device irq to get the INTC orgate input pins. However, some devices use the continuous bits number in the same orgate. To reduce the enumerated device id definition, create a new API to get the INTC orgate index and source bit number if users only provide the start bus number of device. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 4257b5e8af..0bbd66110b 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -164,6 +164,11 @@ struct gic_intc_irq_info { const int *ptr; }; +struct gic_intc_orgate_info { + int index; + int int_num; +}; + static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = { {128, aspeed_soc_ast2700_gic128_intcmap}, {129, NULL}, @@ -193,6 +198,27 @@ static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); } +static void aspeed_soc_ast2700_get_intc_orgate(AspeedSoCState *s, int dev, + struct gic_intc_orgate_info *orgate_info) +{ + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); + int i; + + for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { + if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { + assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); + orgate_info->index = i; + orgate_info->int_num = aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]; + return; + } + } + + /* + * Invalid orgate index, device irq should be 128 to 136. + */ + g_assert_not_reached(); +} + static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, unsigned int size) {