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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f3f4592esm45107766b.26.2024.08.13.00.13.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Aug 2024 00:13:57 -0700 (PDT) From: Andrew Jones To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bmeng.cn@gmail.com, zong.li@sifive.com, liwei1518@gmail.com, cwshu@andestech.com, dbarboza@ventanamicro.com Subject: [PATCH] target/riscv32: Fix masking of physical address Date: Tue, 13 Aug 2024 09:13:56 +0200 Message-ID: <20240813071355.310710-2-ajones@ventanamicro.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org C doesn't extend the sign bit for unsigned types since there isn't a sign bit to extend. This means a promotion of a u32 to a u64 results in the upper 32 bits of the u64 being zero. If that result is then used as a mask on another u64 the upper 32 bits will be cleared. rv32 physical addresses may be up to 34 bits wide, so we don't want to clear the high bits while page aligning the address. The fix is to revert to using target_long, since a signed type will get extended. Fixes: af3fc195e3c8 ("target/riscv: Change the TLB page size depends on PMP entries.") Signed-off-by: Andrew Jones --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 395a1d914061..dfef1b20d1e8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1323,7 +1323,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, int ret = TRANSLATE_FAIL; int mode = mmuidx_priv(mmu_idx); /* default TLB page size */ - target_ulong tlb_size = TARGET_PAGE_SIZE; + target_long tlb_size = TARGET_PAGE_SIZE; env->guest_phys_fault_addr = 0;