| Message ID | 20240816010711.3055425-7-debug@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv support for control flow integrity extensions | expand |
On 8/16/24 11:07, Deepak Gupta wrote: > Implements setting lp expected when `jalr` is encountered and implements > `lpad` instruction of zicfilp. `lpad` instruction is taken out of > auipc x0, <imm_20>. This is an existing HINTNOP space. If `lpad` is > target of an indirect branch, cpu checks for 20 bit value in x7 upper > with 20 bit value embedded in `lpad`. If they don't match, cpu raises a > sw check exception with tval = 2. > > Signed-off-by: Deepak Gupta <debug@rivosinc.com> > Co-developed-by: Jim Shu <jim.shu@sifive.com> > Co-developed-by: Andy Chiu <andy.chiu@sifive.com> > --- > target/riscv/cpu_user.h | 1 + > target/riscv/insn32.decode | 5 ++- > target/riscv/insn_trans/trans_rvi.c.inc | 53 +++++++++++++++++++++++++ > 3 files changed, 58 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h > index 02afad608b..e6927ff847 100644 > --- a/target/riscv/cpu_user.h > +++ b/target/riscv/cpu_user.h > @@ -15,5 +15,6 @@ > #define xA6 16 > #define xA7 17 /* syscall number for RVI ABI */ > #define xT0 5 /* syscall number for RVE ABI */ > +#define xT2 7 > > #endif > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index c45b8fa1d8..494b6cdcc6 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -123,7 +123,10 @@ sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm > > # *** RV32I Base Instruction Set *** > lui .................... ..... 0110111 @u > -auipc .................... ..... 0010111 @u > +{ > + lpad label:20 00000 0010111 > + auipc .................... ..... 0010111 @u It's often helpful to align the fields. lpad label:20 00000 0010111 auipc .................... ..... 0010111 @u > +static bool trans_lpad(DisasContext *ctx, arg_lpad *a) > +{ > + bool lp_expected = ctx->fcfi_lp_expected; > + /* > + * If zicfilp not present, the encoding is a nop. > + * If forward cfi is not enabled, implementation is a nop. > + */ > + if (!ctx->fcfi_enabled) { > + return true; > + } > + > + if (ctx->base.pc_next == ctx->base.pc_first) { > + ctx->fcfi_lp_expected = false; > + /* If landing pad was expected, PC must be 4 byte aligned */ > + if (lp_expected && ((ctx->base.pc_next) & 0x3)) { > + /* > + * misaligned, according to spec we should raise sw check exception > + */ > + gen_helper_raise_sw_check_excep(tcg_env, > + tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL)); > + return true; > + } > + } > + > + /* if lp was expected and lpad_label non-zero, do label check */ > + if (lp_expected && (a->label != 0)) { This is over-complicated. (1) lp_expected is true if and only if fcfi_enabled is true. (2) if lp_expected is false, the implementation is a nop. Therefore, just begin with if (!ctx->fcfi_lp_expected) { return true; } and drop all other references to lp_expected. (3) lp_expected is true if and only if ctx->base.pc_next == ctx->base.pc_first. Beyond the first instruction of the TranslationBlock, trans_lpad itself will clear lp_expected. It cannot be set again except by ending a TranslationBlock. > + tcg_gen_st_tl(tcg_constant_tl(0), tcg_env, > + offsetof(CPURISCVState, elp)); Incorrect: this stores to target_(u)long, whereas elp is a bool. You need tcg_gen_st8_i32. > + if (ctx->fcfi_enabled) { > + /* > + * return from functions (i.e. rs1 == xRA || rs1 == xT0) are not > + * tracked. zicfilp introduces sw guarded branch as well. sw guarded > + * branch are not tracked. rs1 == xT2 is a sw guarded branch. > + */ > + if (a->rs1 != xRA && a->rs1 != xT0 && a->rs1 != xT2) { > + tcg_gen_st_tl(tcg_constant_tl(1), > + tcg_env, offsetof(CPURISCVState, elp)); Likewise. You may wish to add a utility function to set elp. r~
diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h index 02afad608b..e6927ff847 100644 --- a/target/riscv/cpu_user.h +++ b/target/riscv/cpu_user.h @@ -15,5 +15,6 @@ #define xA6 16 #define xA7 17 /* syscall number for RVI ABI */ #define xT0 5 /* syscall number for RVE ABI */ +#define xT2 7 #endif diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c45b8fa1d8..494b6cdcc6 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -123,7 +123,10 @@ sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u -auipc .................... ..... 0010111 @u +{ + lpad label:20 00000 0010111 + auipc .................... ..... 0010111 @u +} jal .................... ..... 1101111 @j jalr ............ ..... 000 ..... 1100111 @i beq ....... ..... ..... 000 ..... 1100011 @b diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 98e3806d5e..936b430282 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -36,6 +36,47 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a) return true; } +static bool trans_lpad(DisasContext *ctx, arg_lpad *a) +{ + bool lp_expected = ctx->fcfi_lp_expected; + /* + * If zicfilp not present, the encoding is a nop. + * If forward cfi is not enabled, implementation is a nop. + */ + if (!ctx->fcfi_enabled) { + return true; + } + + if (ctx->base.pc_next == ctx->base.pc_first) { + ctx->fcfi_lp_expected = false; + /* If landing pad was expected, PC must be 4 byte aligned */ + if (lp_expected && ((ctx->base.pc_next) & 0x3)) { + /* + * misaligned, according to spec we should raise sw check exception + */ + gen_helper_raise_sw_check_excep(tcg_env, + tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL)); + return true; + } + } + + /* if lp was expected and lpad_label non-zero, do label check */ + if (lp_expected && (a->label != 0)) { + TCGLabel *skip = gen_new_label(); + TCGv tmp = tcg_temp_new(); + tcg_gen_extract_tl(tmp, get_gpr(ctx, xT2, EXT_NONE), 12, 20); + tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->label, skip); + gen_helper_raise_sw_check_excep(tcg_env, + tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL)); + gen_set_label(skip); + } + + tcg_gen_st_tl(tcg_constant_tl(0), tcg_env, + offsetof(CPURISCVState, elp)); + + return true; +} + static bool trans_auipc(DisasContext *ctx, arg_auipc *a) { TCGv target_pc = dest_gpr(ctx, a->rd); @@ -75,6 +116,18 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) gen_set_gpr(ctx, a->rd, succ_pc); tcg_gen_mov_tl(cpu_pc, target_pc); + if (ctx->fcfi_enabled) { + /* + * return from functions (i.e. rs1 == xRA || rs1 == xT0) are not + * tracked. zicfilp introduces sw guarded branch as well. sw guarded + * branch are not tracked. rs1 == xT2 is a sw guarded branch. + */ + if (a->rs1 != xRA && a->rs1 != xT0 && a->rs1 != xT2) { + tcg_gen_st_tl(tcg_constant_tl(1), + tcg_env, offsetof(CPURISCVState, elp)); + } + } + lookup_and_goto_ptr(ctx); if (misaligned) {
Implements setting lp expected when `jalr` is encountered and implements `lpad` instruction of zicfilp. `lpad` instruction is taken out of auipc x0, <imm_20>. This is an existing HINTNOP space. If `lpad` is target of an indirect branch, cpu checks for 20 bit value in x7 upper with 20 bit value embedded in `lpad`. If they don't match, cpu raises a sw check exception with tval = 2. Signed-off-by: Deepak Gupta <debug@rivosinc.com> Co-developed-by: Jim Shu <jim.shu@sifive.com> Co-developed-by: Andy Chiu <andy.chiu@sifive.com> --- target/riscv/cpu_user.h | 1 + target/riscv/insn32.decode | 5 ++- target/riscv/insn_trans/trans_rvi.c.inc | 53 +++++++++++++++++++++++++ 3 files changed, 58 insertions(+), 1 deletion(-)