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([50.37.200.153]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d3e2e6b201sm2134285a91.15.2024.08.16.09.36.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 09:36:55 -0700 (PDT) From: Doug Brown To: Vikram Garhwal , Francisco Iglesias , Pavel Pisa Cc: Jason Wang , qemu-devel@nongnu.org, Doug Brown Subject: [PATCH 5/5] hw/net/can/xlnx-versal-canfd: Handle RX of short FD frames Date: Fri, 16 Aug 2024 09:35:05 -0700 Message-Id: <20240816163504.789393-6-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240816163504.789393-1-doug@schmorgal.com> References: <20240816163504.789393-1-doug@schmorgal.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=doug@schmorgal.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 16 Aug 2024 14:18:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There was no case for handling received CAN FD frames with a DLC of 0-8. This was already handled properly with TX. Add similar code for RX. Signed-off-by: Doug Brown Reviewed-by: Francisco Iglesias --- hw/net/can/xlnx-versal-canfd.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c index fda1e7016a..ce68dab46a 100644 --- a/hw/net/can/xlnx-versal-canfd.c +++ b/hw/net/can/xlnx-versal-canfd.c @@ -1052,10 +1052,15 @@ static void store_rx_sequential(XlnxVersalCANFDState *s, if (frame->flags & QEMU_CAN_FRMF_TYPE_FD) { is_canfd_frame = true; - /* Store dlc value in Xilinx specific format. */ - for (i = 0; i < ARRAY_SIZE(canfd_dlc_array); i++) { - if (canfd_dlc_array[i] == frame->can_dlc) { - dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, 8 + i); + if (dlc <= 8) { + dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, dlc); + } else { + /* Store dlc value in Xilinx specific format. */ + for (i = 0; i < ARRAY_SIZE(canfd_dlc_array); i++) { + if (canfd_dlc_array[i] == frame->can_dlc) { + dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, + 8 + i); + } } } } else {