From patchwork Tue Aug 20 00:01:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 13769193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7F62C52D6F for ; Tue, 20 Aug 2024 00:03:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sgCKU-0000za-4a; Mon, 19 Aug 2024 20:02:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sgCK1-0000hf-EI for qemu-devel@nongnu.org; Mon, 19 Aug 2024 20:02:02 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sgCJi-0001CH-8E for qemu-devel@nongnu.org; Mon, 19 Aug 2024 20:01:44 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-201fba05363so30915715ad.3 for ; Mon, 19 Aug 2024 17:01:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724112100; x=1724716900; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NjZJpddrUYMLka+s3BuiKelWfoIA0sOQqw+ndLoWex0=; b=Sg89MPfvwpQHR92EDYno4hong48wZduipfdytdI8ZU5tO7v70Mhfe0W6LUFlrEMcxJ YdIDZhJzs96aonkddOkXJBec5rIsFB+4EqN0j7g38PWyBDy63fPeTrml3YRP4ejx5hdk C+/fauWJktYfxdDKwqnWIepPcwm3zeKInQwAGVwwxbiHBpZcbSFHiloHXZo5XeYye5T4 BXa610gVFpUNrIa9S7CG1ZyGEenRfyIKidMJfG0jwG3jAtUSN+4xB16ToGIEOT7Ut9Se aMVZoAyeAWRJUY2kZECzhWoua7C1ctrpoiMWQ6MciC4pLkaI7lHO2zFnH0gjW+KDZ8uc jQNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724112100; x=1724716900; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NjZJpddrUYMLka+s3BuiKelWfoIA0sOQqw+ndLoWex0=; b=G7H4lO8pREQBPaUSCsffJFsvrzHS+Hny+iS+SealE7bFtLjm4phl2PSNpVcos1j5Me UFGcvs0hcfyqnJZW5cDScCEO06vzhP6qtAHZ8NWQBNGGc02qwm55HQWCPeQXw5u0GTOZ vv0P320kWylP7Z4CIgbsp1JvRESG0B/AB+J97Y+P6tbjRraoteW5phDkxtGcYi2D2n8e qS+DVcSpRaRsoDThWYrg4G6N84OJDn+VeOTuGd1+Vmsz04HTwaMmRc5dP4tBDPNB/gKg NFZLQhaPRwcD8RyUO/srt6rfqszB+PHMuP+Up4qHE9aMw7LPKdnGiVZt05Cu/AwNcpKf skOg== X-Forwarded-Encrypted: i=1; AJvYcCXHMLDODogXVMDGmv+1Bcyh4Pmk1TpXj5slyqhFKznpZYqkTP3QtxJE3q/1MqBGIVOdFF2L07aBoHXEjxBvlDk4wjg9Um0= X-Gm-Message-State: AOJu0YxlgNh1d5aH8jsY+q+q0R8ineKcQWMJp1LChP2aSGIBx+KRReoe qNMhYs5JN5DiQ0owxsV54feVVd8wYfR5PzEpXiPQKwch98IVJNoy+5NklCdW1Og= X-Google-Smtp-Source: AGHT+IFjJmeKFNTpI7h2BL4lax4R4H1tL+tz8V8bPl2zPVJwL5AAL5k15L+Dg3vmHVpqdaHHaazBog== X-Received: by 2002:a17:903:228a:b0:1fb:1cc3:6482 with SMTP id d9443c01a7336-20203f32206mr121336605ad.45.1724112100118; Mon, 19 Aug 2024 17:01:40 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f038a779sm67477445ad.188.2024.08.19.17.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2024 17:01:39 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com, Deepak Gupta , Richard Henderson Subject: [PATCH v5 04/15] target/riscv: additional code information for sw check Date: Mon, 19 Aug 2024 17:01:18 -0700 Message-ID: <20240820000129.3522346-5-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240820000129.3522346-1-debug@rivosinc.com> References: <20240820000129.3522346-1-debug@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=debug@rivosinc.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org sw check exception support was recently added. This patch further augments sw check exception by providing support for additional code which is provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever sw check exception is raised *tval gets the value deposited in `sw_check_code`. Signed-off-by: Deepak Gupta Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 2 ++ target/riscv/csr.c | 1 + 3 files changed, 5 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7be0fa30f7..11c6513a90 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -224,6 +224,8 @@ struct CPUArchState { /* elp state for zicfilp extension */ bool elp; + /* sw check code for sw check exception */ + target_ulong sw_check_code; #ifdef CONFIG_USER_ONLY uint32_t elf_flags; bool ufcfien; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 12484ca7d2..9f08a67a9e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1761,6 +1761,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) cs->watchpoint_hit = NULL; } break; + case RISCV_EXCP_SW_CHECK: + tval = env->sw_check_code; default: break; } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5771a14848..a5a969a377 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1179,6 +1179,7 @@ static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ + (1ULL << (RISCV_EXCP_SW_CHECK)) | \ (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \