| Message ID | 20240823003231.3522113-1-alistair.francis@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target: riscv: Enable Bit Manip for OpenTitan Ibex CPU | expand |
On 8/22/24 9:32 PM, Alistair Francis wrote: > The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc > and Zbs bit-manipulation sub-extensions ratified in > v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable > them in QEMU as well. > > 1: https://github.com/lowRISC/opentitan/pull/9748 > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a90808a3ba..7e13fb2c0f 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -701,6 +701,11 @@ static void rv32_ibex_cpu_init(Object *obj) > cpu->cfg.ext_zicsr = true; > cpu->cfg.pmp = true; > cpu->cfg.ext_smepmp = true; > + > + cpu->cfg.ext_zba = true; > + cpu->cfg.ext_zbb = true; > + cpu->cfg.ext_zbc = true; > + cpu->cfg.ext_zbs = true; > } > > static void rv32_imafcu_nommu_cpu_init(Object *obj)
On Fri, Aug 23, 2024 at 10:32 AM Alistair Francis <alistair23@gmail.com> wrote: > > The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc > and Zbs bit-manipulation sub-extensions ratified in > v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable > them in QEMU as well. > > 1: https://github.com/lowRISC/opentitan/pull/9748 > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a90808a3ba..7e13fb2c0f 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -701,6 +701,11 @@ static void rv32_ibex_cpu_init(Object *obj) > cpu->cfg.ext_zicsr = true; > cpu->cfg.pmp = true; > cpu->cfg.ext_smepmp = true; > + > + cpu->cfg.ext_zba = true; > + cpu->cfg.ext_zbb = true; > + cpu->cfg.ext_zbc = true; > + cpu->cfg.ext_zbs = true; > } > > static void rv32_imafcu_nommu_cpu_init(Object *obj) > -- > 2.46.0 >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a90808a3ba..7e13fb2c0f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -701,6 +701,11 @@ static void rv32_ibex_cpu_init(Object *obj) cpu->cfg.ext_zicsr = true; cpu->cfg.pmp = true; cpu->cfg.ext_smepmp = true; + + cpu->cfg.ext_zba = true; + cpu->cfg.ext_zbb = true; + cpu->cfg.ext_zbc = true; + cpu->cfg.ext_zbs = true; } static void rv32_imafcu_nommu_cpu_init(Object *obj)
The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc and Zbs bit-manipulation sub-extensions ratified in v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable them in QEMU as well. 1: https://github.com/lowRISC/opentitan/pull/9748 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 5 +++++ 1 file changed, 5 insertions(+)