From patchwork Fri Aug 23 19:01:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 13775734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B00ADC5321E for ; Fri, 23 Aug 2024 19:04:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1shZYE-0004ot-T9; Fri, 23 Aug 2024 15:02:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1shZXr-0003Pj-U7 for qemu-devel@nongnu.org; Fri, 23 Aug 2024 15:02:00 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1shZXp-0004LF-6M for qemu-devel@nongnu.org; Fri, 23 Aug 2024 15:01:58 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-20208830de8so18978755ad.1 for ; Fri, 23 Aug 2024 12:01:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724439716; x=1725044516; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N4mAJdMCJKnSHTZBg24BmY/PI6LJMup/le/nWxFZ0Nw=; b=CR3KdZ/OPX+W8Eun6ZWJwCWrm8quYaT0Vw8hsN6pYNcHQTywfWpuVhrg02GPC9zz6Y w2SdXFMUZqtHEni378jrAE5eOmIkDbL01OJtx+QlPX2L7lZFj9J8UqrcDQKmAj4rIMRn a7gt7ZAnyGmus+cDKQrHjEXba/lBQVCBMvN4+ODpI8CznmcSrvJ6z9KEVrRJ9/FjWm4T B5cmpU2KxW0w8rakq76fNj9sEByJTTJOmh6uKIap6iBC4z9QRW2CbZZqjZSWV21XVaN6 r1AFBDf22A+8sp/VEADLgS1qj5XbSDEnEEwOVZqUOX+M91CktkjEVth2MVXyqONn3AGy TCHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724439716; x=1725044516; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N4mAJdMCJKnSHTZBg24BmY/PI6LJMup/le/nWxFZ0Nw=; b=S94WMpDwlDVdNgWL12Acq/vIHq3KFB9+tlEWtjHUMoC1q5ijoYy50e0QSKUtr7GyAa W9lj9CSMk36pN6toRL2V3p5xdxZxSPb3NevnZU+vZ9DbAOcqMlBKtseMbtZZFY8k9l21 vj3h4kQ9yzz/DOmboAVZXayvydZg2RyLYqXVVXaxU6hoS12ltmU1iS1atCe8hrzuP6pB aeh7oiXyfNDrrN2eR7kkjREwS0KaGdeGlpIz83IdrBn88KB3m0lP0p4/nz6HrzcSQ67D 4L6GlKKcG/2I3Mqmt1SSf+SsbdxVqJsiZOvLSb9PYFSDLdgCybfKWWX4rrmtkRQxIvwn QZdw== X-Forwarded-Encrypted: i=1; AJvYcCVdhQmd8uhXg81GNXXgLlDA3G1IU4Ti/ec9iApQLGWN2x0r7ag7X73JEPYeEQXnG1ANPD2xwN/+KMhl@nongnu.org X-Gm-Message-State: AOJu0YzgYHqEPqq5PfFg669ikzh6EHZLnGgtHzaX9z8ZxfG1PpdoeYNP rY6nyxaBIOkXvovIEWTdY+nNMqjllT0IxmrdUrTr3bCH7cBBtIXxAKVnW8Q2I+s= X-Google-Smtp-Source: AGHT+IHB0z/i7ZOeGjJoK0KHgsooxOPO7Fe2dTRAhdR+SSWQHlAlN9FCVBbCy+s9TK1Z7QOyoqHw1w== X-Received: by 2002:a17:902:f550:b0:1fd:a27d:e2ce with SMTP id d9443c01a7336-2039e4ef22bmr43212875ad.49.1724439715622; Fri, 23 Aug 2024 12:01:55 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-203b0c37768sm1749885ad.230.2024.08.23.12.01.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Aug 2024 12:01:53 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, andy.chiu@sifive.com, richard.henderson@linaro.org, kito.cheng@sifive.com, Deepak Gupta Subject: [PATCH v8 08/17] target/riscv: Add zicfiss extension Date: Fri, 23 Aug 2024 12:01:30 -0700 Message-ID: <20240823190140.4156920-9-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240823190140.4156920-1-debug@rivosinc.com> References: <20240823190140.4156920-1-debug@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=debug@rivosinc.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org zicfiss [1] riscv cpu extension enables backward control flow integrity. This patch sets up space for zicfiss extension in cpuconfig. And imple- ments dependency on A, zicsr, zimop and zcmop extensions. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu Co-developed-by: Andy Chiu --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 19 +++++++++++++++++++ 3 files changed, 22 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 083d405516..10a2a32345 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -107,6 +107,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp), + ISA_EXT_DATA_ENTRY(zicfiss, PRIV_VERSION_1_13_0, ext_zicfiss), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr), @@ -1482,6 +1483,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false), + MULTI_EXT_CFG_BOOL("zicfiss", ext_zicfiss, false), MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 88d5defbb5..2499f38407 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -68,6 +68,7 @@ struct RISCVCPUConfig { bool ext_zicbop; bool ext_zicboz; bool ext_zicfilp; + bool ext_zicfiss; bool ext_zicond; bool ext_zihintntl; bool ext_zihintpause; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ed19586c9d..4da26cb926 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -618,6 +618,25 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu->cfg.ext_zihpm = false; } + if (cpu->cfg.ext_zicfiss) { + if (!cpu->cfg.ext_zicsr) { + error_setg(errp, "zicfiss extension requires zicsr extension"); + return; + } + if (!riscv_has_ext(env, RVA)) { + error_setg(errp, "zicfiss extension requires A extension"); + return; + } + if (!cpu->cfg.ext_zimop) { + error_setg(errp, "zicfiss extension requires zimop extension"); + return; + } + if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { + error_setg(errp, "zicfiss with zca requires zcmop extension"); + return; + } + } + if (!cpu->cfg.ext_zihpm) { cpu->cfg.pmu_mask = 0; cpu->pmu_avail_ctrs = 0;