[v2,4/7] hw/net/can/xlnx-versal-canfd: Handle flags correctly

Commit Message

Doug Brown Aug. 27, 2024, 3:49 a.m. UTC

Add support for QEMU_CAN_FRMF_ESI and QEMU_CAN_FRMF_BRS flags, and
ensure frame->flags is always initialized to 0.

Note that the Xilinx IP core doesn't allow manually setting the ESI bit
during transmits, so it's only implemented for the receive case.

Signed-off-by: Doug Brown <[e-mail]>
---
 hw/net/can/xlnx-versal-canfd.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

Comments

Pavel Pisa Aug. 29, 2024, 1:13 p.m. UTC | #1

On Tuesday 27 of August 2024 05:49:24 Doug Brown wrote:
> Add support for QEMU_CAN_FRMF_ESI and QEMU_CAN_FRMF_BRS flags, and
> ensure frame->flags is always initialized to 0.
>
> Note that the Xilinx IP core doesn't allow manually setting the ESI bit
> during transmits, so it's only implemented for the receive case.
>
> Signed-off-by: Doug Brown <[e-mail]>

Reviewed-by: Pavel Pisa <[e-mail]>

Patch

diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c
index 1704b558d0..47631917ab 100644
--- a/hw/net/can/xlnx-versal-canfd.c
+++ b/hw/net/can/xlnx-versal-canfd.c
@@ -872,6 +872,8 @@  static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame,
     uint32_t id_reg_val = 0;
     bool is_rtr = false;
 
+    frame->flags = 0;
+
     /* Check that reg_num should be within TX register space. */
     assert(reg_num <= R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE *
                                           s->cfg.tx_fifo));
@@ -913,7 +915,7 @@  static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame,
          *  15                         49 - 64
          */
 
-        frame->flags = QEMU_CAN_FRMF_TYPE_FD;
+        frame->flags |= QEMU_CAN_FRMF_TYPE_FD;
 
         if (dlc_value < 8) {
             frame->can_dlc = dlc_value;
@@ -921,6 +923,10 @@  static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame,
             assert((dlc_value - 8) < ARRAY_SIZE(canfd_dlc_array));
             frame->can_dlc = canfd_dlc_array[dlc_value - 8];
         }
+
+        if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, BRS)) {
+            frame->flags |= QEMU_CAN_FRMF_BRS;
+        }
     } else {
         /*
          * FD Format bit not set that means it is a CAN Frame.
@@ -1058,6 +1064,13 @@  static void store_rx_sequential(XlnxVersalCANFDState *s,
                     dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, 8 + i);
                 }
             }
+
+            if (frame->flags & QEMU_CAN_FRMF_BRS) {
+                dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, BRS, 1);
+            }
+            if (frame->flags & QEMU_CAN_FRMF_ESI) {
+                dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, ESI, 1);
+            }
         } else {
             is_canfd_frame = false;