| Message ID | 20240827231906.553327-12-debug@rivosinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | riscv support for control flow integrity extensions | expand |
On Wed, Aug 28, 2024 at 9:20 AM Deepak Gupta <debug@rivosinc.com> wrote: > > zicfiss [1] riscv cpu extension enables backward control flow integrity. > > This patch sets up space for zicfiss extension in cpuconfig. And imple- > ments dependency on A, zicsr, zimop and zcmop extensions. > > [1] - https://github.com/riscv/riscv-cfi > > Signed-off-by: Deepak Gupta <debug@rivosinc.com> > Co-developed-by: Jim Shu <jim.shu@sifive.com> > Co-developed-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu_cfg.h | 1 + > target/riscv/tcg/tcg-cpu.c | 19 +++++++++++++++++++ > 3 files changed, 21 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 8e1f05e5b1..0dab110a3f 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -107,6 +107,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11), > ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, has_priv_1_11), > ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp), > + ISA_EXT_DATA_ENTRY(zicfiss, PRIV_VERSION_1_13_0, ext_zicfiss), > ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), > ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), > ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 88d5defbb5..2499f38407 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -68,6 +68,7 @@ struct RISCVCPUConfig { > bool ext_zicbop; > bool ext_zicboz; > bool ext_zicfilp; > + bool ext_zicfiss; > bool ext_zicond; > bool ext_zihintntl; > bool ext_zihintpause; > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index ed19586c9d..4da26cb926 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -618,6 +618,25 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > cpu->cfg.ext_zihpm = false; > } > > + if (cpu->cfg.ext_zicfiss) { > + if (!cpu->cfg.ext_zicsr) { > + error_setg(errp, "zicfiss extension requires zicsr extension"); > + return; > + } > + if (!riscv_has_ext(env, RVA)) { > + error_setg(errp, "zicfiss extension requires A extension"); > + return; > + } > + if (!cpu->cfg.ext_zimop) { > + error_setg(errp, "zicfiss extension requires zimop extension"); > + return; > + } > + if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { > + error_setg(errp, "zicfiss with zca requires zcmop extension"); > + return; > + } > + } > + > if (!cpu->cfg.ext_zihpm) { > cpu->cfg.pmu_mask = 0; > cpu->pmu_avail_ctrs = 0; > -- > 2.44.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8e1f05e5b1..0dab110a3f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -107,6 +107,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp), + ISA_EXT_DATA_ENTRY(zicfiss, PRIV_VERSION_1_13_0, ext_zicfiss), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 88d5defbb5..2499f38407 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -68,6 +68,7 @@ struct RISCVCPUConfig { bool ext_zicbop; bool ext_zicboz; bool ext_zicfilp; + bool ext_zicfiss; bool ext_zicond; bool ext_zihintntl; bool ext_zihintpause; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ed19586c9d..4da26cb926 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -618,6 +618,25 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu->cfg.ext_zihpm = false; } + if (cpu->cfg.ext_zicfiss) { + if (!cpu->cfg.ext_zicsr) { + error_setg(errp, "zicfiss extension requires zicsr extension"); + return; + } + if (!riscv_has_ext(env, RVA)) { + error_setg(errp, "zicfiss extension requires A extension"); + return; + } + if (!cpu->cfg.ext_zimop) { + error_setg(errp, "zicfiss extension requires zimop extension"); + return; + } + if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { + error_setg(errp, "zicfiss with zca requires zcmop extension"); + return; + } + } + if (!cpu->cfg.ext_zihpm) { cpu->cfg.pmu_mask = 0; cpu->pmu_avail_ctrs = 0;
zicfiss [1] riscv cpu extension enables backward control flow integrity. This patch sets up space for zicfiss extension in cpuconfig. And imple- ments dependency on A, zicsr, zimop and zcmop extensions. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta <debug@rivosinc.com> Co-developed-by: Jim Shu <jim.shu@sifive.com> Co-developed-by: Andy Chiu <andy.chiu@sifive.com> --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 19 +++++++++++++++++++ 3 files changed, 21 insertions(+)