From patchwork Wed Aug 28 09:52:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13781026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC761C54E65 for ; Wed, 28 Aug 2024 09:56:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sjFMV-00023V-G9; Wed, 28 Aug 2024 05:53:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sjFMS-0001xp-Dl for qemu-devel@nongnu.org; Wed, 28 Aug 2024 05:53:09 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sjFMQ-0001oN-IU for qemu-devel@nongnu.org; Wed, 28 Aug 2024 05:53:08 -0400 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-656d8b346d2so3921405a12.2 for ; Wed, 28 Aug 2024 02:53:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724838784; x=1725443584; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q8SeRNxqA0kdGYXuMPPKRU3j4MVX/4+712bEYl1oABA=; b=nipOaqizqXm11mnpxNboXbor4g8QTL2gb8cvF+QoxZvzpbylFWx12eDVx5+byx3OMx QWMYhl8/klIsYLwTqJDvdfmVvA0CayeB6ZWH4y+M6GXGeBw+vD0K0ZBVSlMwXjXR4Qxw hH4/YrEDvv0RIeoI5LM8j2KfqHcdrh8EnUr1w9WnuhluXlP7Qf0lIF/s9ozEDKkox3Y+ TfHpTuirXU/ziOuZ7X4Y9Ss7mLIIpn1CEuz74DjundQqwxYNytidhuJlxSBHxMgnfhDa 9po71w1GeK8SWmHkIqFiwFYO+MrMaI8pPlEuXHrTIj9pzvA73zN1+dd+LJA8T47EYIb7 2zXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724838784; x=1725443584; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q8SeRNxqA0kdGYXuMPPKRU3j4MVX/4+712bEYl1oABA=; b=WjlIEREJnSPNQGzGnCC1xUe2ia3gpe1+ccxgXcfaun2+L43m1ZAHzfh7fDAzCqHOHD He39WpFMN2oMy3YC6b/BlzXQvVkwJEmlv9hzW5F2wpJj1S/lEn4uyPbu7eCASs0H7oEH O7bslyWR5Ps9XI8An6JvaiEru5FQM4br6n3AlfY7GipVTD/nzkeour5YSEtW7Vos4SE3 0gBp5GcSO545xbU8qQ50psKHpblNeCBPxe71vxr0K1xU2dLD1lZUHaQYbzzmqnHn/TeR X/viuM0yZtIsl/d3nYFkSV+JO3Ns42Do4M+UcjG1uh0bEpx0ru8Wc+dJ2IfGl+ZnqsCC FgKw== X-Gm-Message-State: AOJu0YxjZ63KlWSjCgSZlsB6pqB4rM2tFwAuaGiXLpNySq/G9CZjIZ7a JJ0eMV0aZgvDVKJSybuwPo+me+ghYe7YH+MQ6fPFS1RSooGOrHgvooHZup8z X-Google-Smtp-Source: AGHT+IHE7ZCAZdcCsTYcgpVVGoE19yB+ZVfV1AbPLA61aNJH4aSfN3AI0BltMdJB5IENWucm7JzCeQ== X-Received: by 2002:a05:6a21:1584:b0:1ca:cbf5:5b0 with SMTP id adf61e73a8af0-1cc8b459221mr15988881637.21.1724838783884; Wed, 28 Aug 2024 02:53:03 -0700 (PDT) Received: from localhost.localdomain ([220.253.126.131]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7143430f6e7sm9787508b3a.160.2024.08.28.02.53.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2024 02:53:03 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Mark Corbin , Warner Losh , Ajeet Singh , Richard Henderson Subject: [PATCH v4 04/17] bsd-user: Implement RISC-V TLS register setup Date: Wed, 28 Aug 2024 19:52:30 +1000 Message-Id: <20240828095243.90491-5-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240828095243.90491-1-itachis@FreeBSD.org> References: <20240828095243.90491-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=itachis6234@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch.h | 27 +++++++++++++++++++++++++++ bsd-user/riscv/target_arch_cpu.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 bsd-user/riscv/target_arch.h create mode 100644 bsd-user/riscv/target_arch_cpu.c diff --git a/bsd-user/riscv/target_arch.h b/bsd-user/riscv/target_arch.h new file mode 100644 index 0000000000..26ce07f343 --- /dev/null +++ b/bsd-user/riscv/target_arch.h @@ -0,0 +1,27 @@ +/* + * RISC-V specific prototypes + * + * Copyright (c) 2019 Mark Corbin + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_H +#define TARGET_ARCH_H + +#include "qemu.h" + +void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls); + +#endif /* TARGET_ARCH_H */ diff --git a/bsd-user/riscv/target_arch_cpu.c b/bsd-user/riscv/target_arch_cpu.c new file mode 100644 index 0000000000..44e25d2ddf --- /dev/null +++ b/bsd-user/riscv/target_arch_cpu.c @@ -0,0 +1,29 @@ +/* + * RISC-V CPU related code + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ +#include "qemu/osdep.h" + +#include "target_arch.h" + +#define TP_OFFSET 16 + +/* Compare with cpu_set_user_tls() in riscv/riscv/vm_machdep.c */ +void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls) +{ + env->gpr[xTP] = newtls + TP_OFFSET; +}