From patchwork Wed Aug 28 09:52:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13781027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DAA0FC5479A for ; Wed, 28 Aug 2024 09:57:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sjFMZ-0002Hv-6i; Wed, 28 Aug 2024 05:53:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sjFMW-00028Q-NG for qemu-devel@nongnu.org; Wed, 28 Aug 2024 05:53:12 -0400 Received: from mail-oo1-xc2d.google.com ([2607:f8b0:4864:20::c2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sjFMU-0001oq-NQ for qemu-devel@nongnu.org; Wed, 28 Aug 2024 05:53:12 -0400 Received: by mail-oo1-xc2d.google.com with SMTP id 006d021491bc7-5dc93fa5639so4846348eaf.1 for ; Wed, 28 Aug 2024 02:53:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724838789; x=1725443589; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a+NCEiOZJzboz9w1INUibK6hoUbq+IVFPstbDaWXows=; b=HxqKT21iD3bknQ5yTO/MUvJ4Yv7obeAaz+wAUBsPz7bO8B4vZQnkEf+wB69st4PR9o bNbEgjOQG0vWQDFTC2U28dpYAV9aAzxObBelIoCup9xFNTZ/Rw2EHGBo0I7kOL6tw1CS UvRFaU0cscoEoKaZVkzJYyiI5R5l/9k+4h1MnB4lmlY/N+eN9q4FOhQD50t7r62pIn4s WsLqwkbwsIusOIrGS0P5xO+5L90ng/mEhYMP8xKHNDY3gcfY0LgSsHKiOVkEHcENH8b/ Q39j1gG/qI/VHtDITbLyim5nBoPzgegGY4RdfFSwvz3BccP7BGLJTFSuJqeM7NBNmSOk nkvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724838789; x=1725443589; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a+NCEiOZJzboz9w1INUibK6hoUbq+IVFPstbDaWXows=; b=ee4O0s1q1Cpb7TVWOup5pd8qV1VL1W8+OOVgoJdng9MVv3nTuQ6U2J2FQs/NLlJdDy eTkaDnOKlEh92QOHEn3hgBhwwkHQ4LsVA5r7Z7Ni92o1Ut6db7Q7IeYWxUN8VxAm6J0x oxOKNfiPKd0UI5Y0E7cGKl+BaNmI+KJJHLgpe8l2hZGdTX0fW8bLklXB6kxjoCnhM8L/ coCR6MGmQvyRWtcfTn0r8lEgxbJxfdnShvu6gCjV2TZyP4nqMLCnzYEUWEvp7LHhPhJg dU/j/o+QRBl2YXqnzQRYrrJLQ9RQ/l29BQhIalhaqfn8wf3MH7sa3ei7wC+vx/RfGGiv zjhw== X-Gm-Message-State: AOJu0Yz6s/1z+8+LQWgk71+7qb8FRxzzlz9SfxKcaL6hU1xdkV/0qXm7 FJBp/WhJjj2SfUAjP0384UOsGzf77YdL0e+oVg84PaSnNFJNmfxury2a3m5h X-Google-Smtp-Source: AGHT+IFeVAmuBlc8Lm+LPWhRzOKqi02uvzhAItRjpNJ2Bqtt8oZbOHVyOTNv0sSaDQLV3Qdr1zFb2A== X-Received: by 2002:a05:6358:57a3:b0:1ac:f109:e248 with SMTP id e5c5f4694b2df-1b5c3a458a8mr1878612555d.2.1724838789022; Wed, 28 Aug 2024 02:53:09 -0700 (PDT) Received: from localhost.localdomain ([220.253.126.131]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7143430f6e7sm9787508b3a.160.2024.08.28.02.53.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2024 02:53:08 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Mark Corbin , Warner Losh , Ajeet Singh , Richard Henderson Subject: [PATCH v4 06/17] bsd-user: Define RISC-V register structures and register copying Date: Wed, 28 Aug 2024 19:52:32 +1000 Message-Id: <20240828095243.90491-7-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240828095243.90491-1-itachis@FreeBSD.org> References: <20240828095243.90491-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=itachis6234@gmail.com; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Added definitions for RISC-V register structures, including general-purpose registers and floating-point registers, in 'target_arch_reg.h'. Implemented the 'target_copy_regs' function to copy register values from the CPU state to the target register structure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_reg.h | 88 ++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 bsd-user/riscv/target_arch_reg.h diff --git a/bsd-user/riscv/target_arch_reg.h b/bsd-user/riscv/target_arch_reg.h new file mode 100644 index 0000000000..12b1c96b61 --- /dev/null +++ b/bsd-user/riscv/target_arch_reg.h @@ -0,0 +1,88 @@ +/* + * RISC-V register structures + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_REG_H +#define TARGET_ARCH_REG_H + +/* Compare with riscv/include/reg.h */ +typedef struct target_reg { + uint64_t ra; /* return address */ + uint64_t sp; /* stack pointer */ + uint64_t gp; /* global pointer */ + uint64_t tp; /* thread pointer */ + uint64_t t[7]; /* temporaries */ + uint64_t s[12]; /* saved registers */ + uint64_t a[8]; /* function arguments */ + uint64_t sepc; /* exception program counter */ + uint64_t sstatus; /* status register */ +} target_reg_t; + +typedef struct target_fpreg { + uint64_t fp_x[32][2]; /* Floating point registers */ + uint64_t fp_fcsr; /* Floating point control reg */ +} target_fpreg_t; + +#define tswapreg(ptr) tswapal(ptr) + +/* Compare with struct trapframe in riscv/include/frame.h */ +static inline void target_copy_regs(target_reg_t *regs, + const CPURISCVState *env) +{ + + regs->ra = tswapreg(env->gpr[1]); + regs->sp = tswapreg(env->gpr[2]); + regs->gp = tswapreg(env->gpr[3]); + regs->tp = tswapreg(env->gpr[4]); + + regs->t[0] = tswapreg(env->gpr[5]); + regs->t[1] = tswapreg(env->gpr[6]); + regs->t[2] = tswapreg(env->gpr[7]); + regs->t[3] = tswapreg(env->gpr[28]); + regs->t[4] = tswapreg(env->gpr[29]); + regs->t[5] = tswapreg(env->gpr[30]); + regs->t[6] = tswapreg(env->gpr[31]); + + regs->s[0] = tswapreg(env->gpr[8]); + regs->s[1] = tswapreg(env->gpr[9]); + regs->s[2] = tswapreg(env->gpr[18]); + regs->s[3] = tswapreg(env->gpr[19]); + regs->s[4] = tswapreg(env->gpr[20]); + regs->s[5] = tswapreg(env->gpr[21]); + regs->s[6] = tswapreg(env->gpr[22]); + regs->s[7] = tswapreg(env->gpr[23]); + regs->s[8] = tswapreg(env->gpr[24]); + regs->s[9] = tswapreg(env->gpr[25]); + regs->s[10] = tswapreg(env->gpr[26]); + regs->s[11] = tswapreg(env->gpr[27]); + + regs->a[0] = tswapreg(env->gpr[10]); + regs->a[1] = tswapreg(env->gpr[11]); + regs->a[2] = tswapreg(env->gpr[12]); + regs->a[3] = tswapreg(env->gpr[13]); + regs->a[4] = tswapreg(env->gpr[14]); + regs->a[5] = tswapreg(env->gpr[15]); + regs->a[6] = tswapreg(env->gpr[16]); + regs->a[7] = tswapreg(env->gpr[17]); + + regs->sepc = tswapreg(env->pc); +} + +#undef tswapreg + +#endif /* TARGET_ARCH_REG_H */