From patchwork Fri Aug 30 06:16:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 13784339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C088CA0EE1 for ; Fri, 30 Aug 2024 06:22:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sjv1Q-0003V0-AH; Fri, 30 Aug 2024 02:22:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sjv1O-0003Lb-KD; Fri, 30 Aug 2024 02:22:10 -0400 Received: from out30-97.freemail.mail.aliyun.com ([115.124.30.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sjv1M-0005bi-1N; Fri, 30 Aug 2024 02:22:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1724998922; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=BHCqwJw5aRewUdGWcWDnnl2zsOtJz7NeqgbD35JXVug=; b=PYix7eiRzY5qM/VDA9Weu85mXvEFtV2HqfrNDAG8URpIcDkV5hT8NuORSY8yEqn5UsKwoSyD6B1X1fxHrlas0nKVfLD8n41nvcZoU29jYNw9neMs1adisJZkKNu3Y4ClF9CwN2W1nrBK6DLDTWfF5rWHdqxEl60ojKEflxDdCTY= Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WDvk4GJ_1724998921) by smtp.aliyun-inc.com; Fri, 30 Aug 2024 14:22:01 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v2 10/14] tcg/riscv: Implement vector sat/mul ops Date: Fri, 30 Aug 2024 14:16:03 +0800 Message-Id: <20240830061607.1940-11-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> References: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Received-SPF: pass client-ip=115.124.30.97; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-97.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 36 ++++++++++++++++++++++++++++++++++++ tcg/riscv/tcg-target.h | 4 ++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 4fc82481a7..01d03a9208 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -323,6 +323,12 @@ typedef enum { OPC_VXOR_VI = 0x2c000057 | V_OPIVI, OPC_VRSUB_VI = 0xc000057 | V_OPIVI, + OPC_VMUL_VV = 0x94000057 | V_OPMVV, + OPC_VSADD_VV = 0x84000057 | V_OPIVV, + OPC_VSSUB_VV = 0x8c000057 | V_OPIVV, + OPC_VSADDU_VV = 0x80000057 | V_OPIVV, + OPC_VSSUBU_VV = 0x88000057 | V_OPIVV, + OPC_VMSEQ_VV = 0x60000057 | V_OPIVV, OPC_VMSEQ_VI = 0x60000057 | V_OPIVI, OPC_VMSEQ_VX = 0x60000057 | V_OPIVX, @@ -2399,6 +2405,26 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, riscv_set_vec_config_vl_vece(s, type, vece); tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a1, 0, true); break; + case INDEX_op_mul_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VMUL_VV, a0, a1, a2, true); + break; + case INDEX_op_ssadd_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VSADD_VV, a0, a1, a2, true); + break; + case INDEX_op_sssub_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VSSUB_VV, a0, a1, a2, true); + break; + case INDEX_op_usadd_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VSADDU_VV, a0, a1, a2, true); + break; + case INDEX_op_ussub_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VSSUBU_VV, a0, a1, a2, true); + break; case INDEX_op_rvv_cmp_vx: riscv_set_vec_config_vl_vece(s, type, vece); tcg_out_cmp_vec_vx(s, a2, a0, a1); @@ -2527,6 +2553,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_xor_vec: case INDEX_op_not_vec: case INDEX_op_neg_vec: + case INDEX_op_mul_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return 1; case INDEX_op_cmp_vec: return -1; @@ -2688,6 +2719,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_and_vec: case INDEX_op_or_vec: case INDEX_op_xor_vec: + case INDEX_op_mul_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return C_O1_I2(v, v, v); case INDEX_op_rvv_merge_vec: return C_O1_I2(v, v, vK); diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 401696d639..21251f8b23 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -160,8 +160,8 @@ typedef enum { #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 -#define TCG_TARGET_HAS_mul_vec 0 -#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_mul_vec 1 +#define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0