| Message ID | 20240904061859.86615-3-maobibo@loongson.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/loongarch: Add loongson binary translation feature | expand |
在 2024/9/4 下午2:18, Bibo Mao 写道: > Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate. > And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added > to save/restore lbt registers. > > Signed-off-by: Bibo Mao <maobibo@loongson.cn> > --- > target/loongarch/cpu.h | 12 ++++++++ > target/loongarch/kvm/kvm.c | 60 ++++++++++++++++++++++++++++++++++++++ > target/loongarch/machine.c | 24 +++++++++++++++ > 3 files changed, 96 insertions(+) > Reviewed-by: Song Gao <gaosong@loongson.cn> Thanks Song Gao
在 2024/9/9 下午7:52, gaosong 写道: > > > 在 2024/9/4 下午2:18, Bibo Mao 写道: >> Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate. >> And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added >> to save/restore lbt registers. >> >> Signed-off-by: Bibo Mao <maobibo@loongson.cn> >> --- >> target/loongarch/cpu.h | 12 ++++++++ >> target/loongarch/kvm/kvm.c | 60 ++++++++++++++++++++++++++++++++++++++ >> target/loongarch/machine.c | 24 +++++++++++++++ >> 3 files changed, 96 insertions(+) >> > > Reviewed-by: Song Gao <gaosong@loongson.cn> > > Thanks > Song Gao Hi, this patch need rebase. Applying: target/loongarch: Implement lbt registers save/restore function error: sha1 information is lacking or useless (target/loongarch/kvm/kvm.c). error: could not build fake ancestor Patch failed at 0001 target/loongarch: Implement lbt registers save/restore function Thanks. Song Gao.
On 2024/9/9 下午9:13, gaosong wrote: > 在 2024/9/9 下午7:52, gaosong 写道: >> >> >> 在 2024/9/4 下午2:18, Bibo Mao 写道: >>> Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate. >>> And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added >>> to save/restore lbt registers. >>> >>> Signed-off-by: Bibo Mao <maobibo@loongson.cn> >>> --- >>> target/loongarch/cpu.h | 12 ++++++++ >>> target/loongarch/kvm/kvm.c | 60 ++++++++++++++++++++++++++++++++++++++ >>> target/loongarch/machine.c | 24 +++++++++++++++ >>> 3 files changed, 96 insertions(+) >>> >> >> Reviewed-by: Song Gao <gaosong@loongson.cn> >> >> Thanks >> Song Gao > Hi, this patch need rebase. > > Applying: target/loongarch: Implement lbt registers save/restore function > error: sha1 information is lacking or useless (target/loongarch/kvm/kvm.c). > error: could not build fake ancestor > Patch failed at 0001 target/loongarch: Implement lbt registers > save/restore function Hi Song, It can apply with the latest qemu version on my side, only that it fails to compile since kvm uapi header files need be updated. LBT patch on qemu side can be skipped here since it depends on LBT patch merged on kernel side firstly. Regards Bibo Mao > > > Thanks. > Song Gao. >
在 2024/9/10 上午10:24, maobibo 写道: > > > On 2024/9/9 下午9:13, gaosong wrote: >> 在 2024/9/9 下午7:52, gaosong 写道: >>> >>> >>> 在 2024/9/4 下午2:18, Bibo Mao 写道: >>>> Six registers scr0 - scr3, eflags and ftop are added in percpu >>>> vmstate. >>>> And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are >>>> added >>>> to save/restore lbt registers. >>>> >>>> Signed-off-by: Bibo Mao <maobibo@loongson.cn> >>>> --- >>>> target/loongarch/cpu.h | 12 ++++++++ >>>> target/loongarch/kvm/kvm.c | 60 >>>> ++++++++++++++++++++++++++++++++++++++ >>>> target/loongarch/machine.c | 24 +++++++++++++++ >>>> 3 files changed, 96 insertions(+) >>>> >>> >>> Reviewed-by: Song Gao <gaosong@loongson.cn> >>> >>> Thanks >>> Song Gao >> Hi, this patch need rebase. >> >> Applying: target/loongarch: Implement lbt registers save/restore >> function >> error: sha1 information is lacking or useless >> (target/loongarch/kvm/kvm.c). >> error: could not build fake ancestor >> Patch failed at 0001 target/loongarch: Implement lbt registers >> save/restore function > > Hi Song, > > It can apply with the latest qemu version on my side, only that it > fails to compile since kvm uapi header files need be updated. > > LBT patch on qemu side can be skipped here since it depends on LBT > patch merged on kernel side firstly. > Hi, The LBT patches already merged on kernel side. Could you update this series and add a patch to support gdb LBT feature ? Thanks. Song Gao > Regards > Bibo Mao >> >> >> Thanks. >> Song Gao. >>
Hi Tiezhu, Does mainline gdb support to dump LBT register now? Regards Bibo Mao On 2024/9/23 下午9:02, gaosong wrote: > 在 2024/9/10 上午10:24, maobibo 写道: >> >> >> On 2024/9/9 下午9:13, gaosong wrote: >>> 在 2024/9/9 下午7:52, gaosong 写道: >>>> >>>> >>>> 在 2024/9/4 下午2:18, Bibo Mao 写道: >>>>> Six registers scr0 - scr3, eflags and ftop are added in percpu >>>>> vmstate. >>>>> And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are >>>>> added >>>>> to save/restore lbt registers. >>>>> >>>>> Signed-off-by: Bibo Mao <maobibo@loongson.cn> >>>>> --- >>>>> target/loongarch/cpu.h | 12 ++++++++ >>>>> target/loongarch/kvm/kvm.c | 60 >>>>> ++++++++++++++++++++++++++++++++++++++ >>>>> target/loongarch/machine.c | 24 +++++++++++++++ >>>>> 3 files changed, 96 insertions(+) >>>>> >>>> >>>> Reviewed-by: Song Gao <gaosong@loongson.cn> >>>> >>>> Thanks >>>> Song Gao >>> Hi, this patch need rebase. >>> >>> Applying: target/loongarch: Implement lbt registers save/restore >>> function >>> error: sha1 information is lacking or useless >>> (target/loongarch/kvm/kvm.c). >>> error: could not build fake ancestor >>> Patch failed at 0001 target/loongarch: Implement lbt registers >>> save/restore function >> >> Hi Song, >> >> It can apply with the latest qemu version on my side, only that it >> fails to compile since kvm uapi header files need be updated. >> >> LBT patch on qemu side can be skipped here since it depends on LBT >> patch merged on kernel side firstly. >> > Hi, > > The LBT patches already merged on kernel side. > Could you update this series and add a patch to support gdb LBT feature ? > > Thanks. > Song Gao > >> Regards >> Bibo Mao >>> >>> >>> Thanks. >>> Song Gao. >>> >
On 09/24/2024 09:28 AM, maobibo wrote: > Hi Tiezhu, > > Does mainline gdb support to dump LBT register now? Yes, here are the related gdb commit and kernel code: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=e4d74c01e773 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/uapi/asm/ptrace.h#n59 Thanks, Tiezhu
On 2024/9/23 下午9:02, gaosong wrote: > 在 2024/9/10 上午10:24, maobibo 写道: >> >> >> On 2024/9/9 下午9:13, gaosong wrote: >>> 在 2024/9/9 下午7:52, gaosong 写道: >>>> >>>> >>>> 在 2024/9/4 下午2:18, Bibo Mao 写道: >>>>> Six registers scr0 - scr3, eflags and ftop are added in percpu >>>>> vmstate. >>>>> And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are >>>>> added >>>>> to save/restore lbt registers. >>>>> >>>>> Signed-off-by: Bibo Mao <maobibo@loongson.cn> >>>>> --- >>>>> target/loongarch/cpu.h | 12 ++++++++ >>>>> target/loongarch/kvm/kvm.c | 60 >>>>> ++++++++++++++++++++++++++++++++++++++ >>>>> target/loongarch/machine.c | 24 +++++++++++++++ >>>>> 3 files changed, 96 insertions(+) >>>>> >>>> >>>> Reviewed-by: Song Gao <gaosong@loongson.cn> >>>> >>>> Thanks >>>> Song Gao >>> Hi, this patch need rebase. >>> >>> Applying: target/loongarch: Implement lbt registers save/restore >>> function >>> error: sha1 information is lacking or useless >>> (target/loongarch/kvm/kvm.c). >>> error: could not build fake ancestor >>> Patch failed at 0001 target/loongarch: Implement lbt registers >>> save/restore function >> >> Hi Song, >> >> It can apply with the latest qemu version on my side, only that it >> fails to compile since kvm uapi header files need be updated. >> >> LBT patch on qemu side can be skipped here since it depends on LBT >> patch merged on kernel side firstly. >> > Hi, > > The LBT patches already merged on kernel side. > Could you update this series and add a patch to support gdb LBT feature ? Hi Song, QEMU TCG does not support LBT, and kernel does not use LBT and it is only saved and restored in kernel mode. gdb can be used to debug user app if there is such requirements. There is no obvious requirement to debug kernel with LBT function, how about adding the function if there is such requirement in future. Regards Bibo Mao > > Thanks. > Song Gao > >> Regards >> Bibo Mao >>> >>> >>> Thanks. >>> Song Gao. >>>
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 2b3f2758f6..0d0a5a58a8 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -286,6 +286,17 @@ enum loongarch_features { LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */ }; +typedef struct LoongArchBT { + /* scratch registers */ + uint64_t scr0; + uint64_t scr1; + uint64_t scr2; + uint64_t scr3; + /* loongarch eflags */ + uint64_t eflags; + uint32_t ftop; +} lbt_t; + typedef struct CPUArchState { uint64_t gpr[32]; uint64_t pc; @@ -293,6 +304,7 @@ typedef struct CPUArchState { fpr_t fpr[32]; bool cf[8]; uint32_t fcsr0; + lbt_t lbt; uint32_t cpucfg[21]; diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index ca56694a81..ed609b9d50 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -477,6 +477,56 @@ static int kvm_loongarch_put_regs_fp(CPUState *cs) return ret; } +static int kvm_loongarch_put_lbt(CPUState *cs) +{ + CPULoongArchState *env = cpu_env(cs); + uint64_t val; + int ret; + + /* check whether vm support LBT firstly */ + if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LBT_ALL) != 7) { + return 0; + } + + /* set six LBT registers including scr0-scr3, eflags, ftop */ + ret = kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR0, &env->lbt.scr0); + ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR1, &env->lbt.scr1); + ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR2, &env->lbt.scr2); + ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR3, &env->lbt.scr3); + ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_EFLAGS, &env->lbt.eflags); + /* + * Be cautious, KVM_REG_LOONGARCH_LBT_FTOP is defined as 64-bit however + * lbt.ftop is 32-bit + */ + val = env->lbt.ftop; + ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_FTOP, &val); + + return ret; +} + +static int kvm_loongarch_get_lbt(CPUState *cs) +{ + CPULoongArchState *env = cpu_env(cs); + uint64_t val; + int ret; + + /* check whether vm support LBT firstly */ + if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LBT_ALL) != 7) { + return 0; + } + + /* get six LBT registers including scr0-scr3, eflags, ftop */ + ret = kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR0, &env->lbt.scr0); + ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR1, &env->lbt.scr1); + ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR2, &env->lbt.scr2); + ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR3, &env->lbt.scr3); + ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_EFLAGS, &env->lbt.eflags); + ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_FTOP, &val); + env->lbt.ftop = (uint32_t)val; + + return ret; +} + void kvm_arch_reset_vcpu(CPULoongArchState *env) { env->mp_state = KVM_MP_STATE_RUNNABLE; @@ -610,6 +660,11 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } + ret = kvm_loongarch_get_lbt(cs); + if (ret) { + return ret; + } + ret = kvm_loongarch_get_mpstate(cs); return ret; } @@ -638,6 +693,11 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } + ret = kvm_loongarch_put_lbt(cs); + if (ret) { + return ret; + } + ret = kvm_loongarch_put_mpstate(cs); return ret; } diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c index 08a7fa5370..04f2eb8ea1 100644 --- a/target/loongarch/machine.c +++ b/target/loongarch/machine.c @@ -110,6 +110,29 @@ static const VMStateDescription vmstate_lasx = { }, }; +static bool lbt_needed(void *opaque) +{ + LoongArchCPU *cpu = opaque; + + return !!FIELD_EX64(cpu->env.cpucfg[2], CPUCFG2, LBT_ALL); +} + +static const VMStateDescription vmstate_lbt = { + .name = "cpu/lbt", + .version_id = 0, + .minimum_version_id = 0, + .needed = lbt_needed, + .fields = (const VMStateField[]) { + VMSTATE_UINT64(env.lbt.scr0, LoongArchCPU), + VMSTATE_UINT64(env.lbt.scr1, LoongArchCPU), + VMSTATE_UINT64(env.lbt.scr2, LoongArchCPU), + VMSTATE_UINT64(env.lbt.scr3, LoongArchCPU), + VMSTATE_UINT64(env.lbt.eflags, LoongArchCPU), + VMSTATE_UINT32(env.lbt.ftop, LoongArchCPU), + VMSTATE_END_OF_LIST() + }, +}; + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool tlb_needed(void *opaque) { @@ -219,6 +242,7 @@ const VMStateDescription vmstate_loongarch_cpu = { #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) &vmstate_tlb, #endif + &vmstate_lbt, NULL } };
Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate. And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added to save/restore lbt registers. Signed-off-by: Bibo Mao <maobibo@loongson.cn> --- target/loongarch/cpu.h | 12 ++++++++ target/loongarch/kvm/kvm.c | 60 ++++++++++++++++++++++++++++++++++++++ target/loongarch/machine.c | 24 +++++++++++++++ 3 files changed, 96 insertions(+)