From patchwork Wed Sep 4 14:27:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 13790988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3658CD37B4 for ; Wed, 4 Sep 2024 14:29:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1slr0w-0000Zh-Ca; Wed, 04 Sep 2024 10:29:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1slr0t-0000GM-LS; Wed, 04 Sep 2024 10:29:39 -0400 Received: from out30-112.freemail.mail.aliyun.com ([115.124.30.112]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1slr0r-0002wx-3a; Wed, 04 Sep 2024 10:29:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1725460172; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=cjn1hPXTauaUJqC2zS5nfB7D68gEHfQ1dhPNriS8qUg=; b=dufoRTCcqdOSGZbye/n7PaKOyKyHWPzp3s4emOtqYZVVBt5oAKjgZUrHutVs11ceJ9dD3TIwoVeJGVcxCrdoAJ74yVEk+dT2soJ6XBsWg0ViwOT+HFXOrwp8Ao+Caypjnw2rqzGYc/T7znGDQgwoAyiQjQHLPTof4CW9Msq7tJ4= Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WEI2Jan_1725460169) by smtp.aliyun-inc.com; Wed, 04 Sep 2024 22:29:31 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v3 02/14] util: Add RISC-V vector extension probe in cpuinfo Date: Wed, 4 Sep 2024 22:27:27 +0800 Message-Id: <20240904142739.854-3-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240904142739.854-1-zhiwei_liu@linux.alibaba.com> References: <20240904142739.854-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Received-SPF: pass client-ip=115.124.30.112; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-112.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: TANG Tiancheng Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation. While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- host/include/riscv/host/cpuinfo.h | 3 +++ util/cpuinfo-riscv.c | 26 ++++++++++++++++++++++++-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpuinfo.h index 2b00660e36..727cb3204b 100644 --- a/host/include/riscv/host/cpuinfo.h +++ b/host/include/riscv/host/cpuinfo.h @@ -10,9 +10,12 @@ #define CPUINFO_ZBA (1u << 1) #define CPUINFO_ZBB (1u << 2) #define CPUINFO_ZICOND (1u << 3) +#define CPUINFO_ZVE64X (1u << 4) /* Initialized with a constructor. */ extern unsigned cpuinfo; +extern unsigned riscv_vlenb; +#define riscv_vlen (riscv_vlenb * 8) /* * We cannot rely on constructor ordering, so other constructors must diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 497ce12680..05917c42d8 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -12,6 +12,7 @@ #endif unsigned cpuinfo; +unsigned riscv_vlenb; static volatile sig_atomic_t got_sigill; static void sigill_handler(int signo, siginfo_t *si, void *data) @@ -33,7 +34,7 @@ static void sigill_handler(int signo, siginfo_t *si, void *data) /* Called both as constructor and (possibly) via other constructors. */ unsigned __attribute__((constructor)) cpuinfo_init(void) { - unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND | CPUINFO_ZVE64X; unsigned info = cpuinfo; if (info) { @@ -49,6 +50,9 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #endif #if defined(__riscv_arch_test) && defined(__riscv_zicond) info |= CPUINFO_ZICOND; +#endif +#if defined(__riscv_arch_test) && defined(__riscv_zve64x) + info |= CPUINFO_ZVE64X; #endif left &= ~info; @@ -64,7 +68,8 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) && pair.key >= 0) { info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; - left &= ~(CPUINFO_ZBA | CPUINFO_ZBB); + info |= pair.value & RISCV_HWPROBE_IMA_V ? CPUINFO_ZVE64X : 0; + left &= ~(CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZVE64X); #ifdef RISCV_HWPROBE_EXT_ZICOND info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; left &= ~CPUINFO_ZICOND; @@ -112,6 +117,23 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) assert(left == 0); } + if (info & CPUINFO_ZVE64X) { + /* + * Get vlenb for Vector: vsetvli rd, x0, e64. + * VLMAX = LMUL * VLEN / SEW. + * The "vsetvli rd, x0, e64" means "LMUL = 1, SEW = 64, rd = VLMAX", + * so "vlenb = VLMAX * 64 / 8". + */ + unsigned long vlmax = 0; + asm volatile(".insn i 0x57, 7, %0, zero, (3 << 3)" : "=r"(vlmax)); + if (vlmax) { + riscv_vlenb = vlmax * 8; + assert(riscv_vlen >= 64 && !(riscv_vlen & (riscv_vlen - 1))); + } else { + info &= ~CPUINFO_ZVE64X; + } + } + info |= CPUINFO_ALWAYS; cpuinfo = info; return info;