| Message ID | 20240908125920.1160236-3-zhao1.liu@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce SMP Cache Topology | expand |
Hi Jonathan, Thanks for your review and feedback! [snip] > > Note, define cache topology based on CPU topology level with two > > reasons: > > > > 1. In practice, a cache will always be bound to the CPU container > > (either private in the CPU container or shared among multiple > > containers), and CPU container is often expressed in terms of CPU > > topology level. > > 2. The x86's cache-related CPUIDs encode cache topology based on APIC > > ID's CPU topology layout. And the ACPI PPTT table that ARM/RISCV > > relies on also requires CPU containers to help indicate the private > > Really trivial but CPU Containers are a different ACPI concept. > For PPTT they are referred to as Processor Groups. Wonderfully they > 'might match a Processor Container in the namespace' which rather implies > they might not. In QEMU they always will because the next bit of the > spec matters. "In that case this entry will match the value of the _UID > method of the associated processor container. Where there is a match it must > be represented." > > So having said all that, CPU container is probably fine as a description. Thanks for the explanation! > > shared hierarchy of the cache. Therefore, for SMP systems, it is > > natural to use the CPU topology hierarchy directly in QEMU to define > > the cache topology. > > > > Suggested-by: Daniel P. Berrange <berrange@redhat.com> > > Signed-off-by: Zhao Liu <zhao1.liu@intel.com> > > Tested-by: Yongwei Ma <yongwei.ma@intel.com> > > Seems fine but my gut would be to combine this and next patch so we can > see how it is used (assuming no one asked for it to be separate!) No problem. I intended to make it easier to review the QAPI part, but these two patches were simple enough that I was happy to combine them. > Version numbers need an update I guess. Ah, yes! > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Thanks! > > +## > > +# @SmpCachePropertiesWrapper: > > +# > > +# List wrapper of SmpCacheProperties. > > +# > > +# @caches: the list of SmpCacheProperties. > > +# > > +# Since 9.1 > > Needs updating to 9.2 I guess. Yes, I think so, too. Thanks, Zhao > > +## > > +{ 'struct': 'SmpCachePropertiesWrapper', > > + 'data': { 'caches': ['SmpCacheProperties'] } } >
diff --git a/qapi/machine-common.json b/qapi/machine-common.json index 148a2c8dccca..f6fe1a208214 100644 --- a/qapi/machine-common.json +++ b/qapi/machine-common.json @@ -63,3 +63,53 @@ { 'enum': 'CpuTopologyLevel', 'data': [ 'invalid', 'thread', 'core', 'module', 'cluster', 'die', 'socket', 'book', 'drawer', 'default' ] } + +## +# @CacheLevelAndType: +# +# Caches a system may have. The enumeration value here is the +# combination of cache level and cache type. +# +# @l1d: L1 data cache. +# +# @l1i: L1 instruction cache. +# +# @l2: L2 (unified) cache. +# +# @l3: L3 (unified) cache +# +# Since: 9.1 +## +{ 'enum': 'CacheLevelAndType', + 'data': [ 'l1d', 'l1i', 'l2', 'l3' ] } + +## +# @SmpCacheProperties: +# +# Cache information for SMP system. +# +# @cache: Cache name, which is the combination of cache level +# and cache type. +# +# @topology: Cache topology level. It accepts the CPU topology +# enumeration as the parameter, i.e., CPUs in the same +# topology container share the same cache. +# +# Since: 9.1 +## +{ 'struct': 'SmpCacheProperties', + 'data': { + 'cache': 'CacheLevelAndType', + 'topology': 'CpuTopologyLevel' } } + +## +# @SmpCachePropertiesWrapper: +# +# List wrapper of SmpCacheProperties. +# +# @caches: the list of SmpCacheProperties. +# +# Since 9.1 +## +{ 'struct': 'SmpCachePropertiesWrapper', + 'data': { 'caches': ['SmpCacheProperties'] } }
The x86 and ARM need to allow user to configure cache properties (current only topology): * For x86, the default cache topology model (of max/host CPU) does not always match the Host's real physical cache topology. Performance can increase when the configured virtual topology is closer to the physical topology than a default topology would be. * For ARM, QEMU can't get the cache topology information from the CPU registers, then user configuration is necessary. Additionally, the cache information is also needed for MPAM emulation (for TCG) to build the right PPTT. Define smp-cache related enumeration and properties in QAPI, so that user could configure cache properties for SMP system through -machine in the subsequent patch. Cache enumeration (CacheLevelAndType) is implemented as the combination of cache level (level 1/2/3) and cache type (data/instruction/unified). Currently, separated L1 cache (L1 data cache and L1 instruction cache) with unified higher-level cache (e.g., unified L2 and L3 caches), is the most common cache architectures. Therefore, enumerate the L1 D-cache, L1 I-cache, L2 cache and L3 cache with smp-cache object to add the basic cache topology support. Other kinds of caches (e.g., L1 unified or L2/L3 separated caches) can be added directly into CacheLevelAndType if necessary. Cache properties (SmpCacheProperties) currently only contains cache topology information, and other cache properties can be added in it if necessary. Note, define cache topology based on CPU topology level with two reasons: 1. In practice, a cache will always be bound to the CPU container (either private in the CPU container or shared among multiple containers), and CPU container is often expressed in terms of CPU topology level. 2. The x86's cache-related CPUIDs encode cache topology based on APIC ID's CPU topology layout. And the ACPI PPTT table that ARM/RISCV relies on also requires CPU containers to help indicate the private shared hierarchy of the cache. Therefore, for SMP systems, it is natural to use the CPU topology hierarchy directly in QEMU to define the cache topology. Suggested-by: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Tested-by: Yongwei Ma <yongwei.ma@intel.com> --- Suggested by credit: * Referred to Daniel's suggestion to introduce cache object list. --- Changes since Patch v1: * Renamed SMPCacheProperty/SMPCacheProperties (QAPI structures) to SmpCacheProperties/SmpCachePropertiesWrapper. (Markus) * Renamed SMPCacheName (QAPI structure) to SmpCacheLevelAndType and dropped prefix. (Markus) * Renamed 'name' field in SmpCacheProperties to 'cache', since the type and level of the cache in SMP system could be able to specify all of these kinds of cache explicitly enough. * Renamed 'topo' field in SmpCacheProperties to 'topology'. (Markus) * Returned error information when user repeats setting cache properties. (Markus) * Renamed SmpCacheLevelAndType to CacheLevelAndType, since this representation is general across SMP or hybrid system. * Dropped handwriten smp-cache object and integrated cache pproperties list into MachineState (in next patch). (Markus) * Added the reason why x86 and ARM need to configure cache information. (Markus and Jonathan) Changes since RFC v2: * New commit to implement cache list with JSON format instead of multiple sub-options in -smp. --- qapi/machine-common.json | 50 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+)