[v2,5/7] i386/cpu: Support thread and module level cache topology

Commit Message

Zhao Liu Sept. 8, 2024, 12:59 p.m. UTC

Allow cache to be defined at the thread and module level. This
increases flexibility for x86 users to customize their cache topology.

Signed-off-by: Zhao Liu <[e-mail]>
Tested-by: Yongwei Ma <[e-mail]>
---
 target/i386/cpu.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

Comments

Zhao Liu Oct. 7, 2024, 11:24 a.m. UTC | #1

On Tue, Sep 17, 2024 at 10:05:08AM +0100, Jonathan Cameron wrote:
> Date: Tue, 17 Sep 2024 10:05:08 +0100
> From: Jonathan Cameron <[e-mail]>
> Subject: Re: [PATCH v2 5/7] i386/cpu: Support thread and module level cache
>  topology
> X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32)
> 
> On Sun,  8 Sep 2024 20:59:18 +0800
> Zhao Liu <[e-mail]> wrote:
> 
> > Allow cache to be defined at the thread and module level. This
> > increases flexibility for x86 users to customize their cache topology.
> > 
> > Signed-off-by: Zhao Liu <[e-mail]>
> > Tested-by: Yongwei Ma <[e-mail]>
>
> Will be interesting to see if anyone uses the thread level, but
> no harm in supporting it.

x86 CPU has a legacy property "x-l1-cache-per-thread". This is the old
QEMU cache topology behavior, kept for compatibility. Now add thread
level and I can refactor the code for this thread level.

> I guess this would be a case of RDT
> / MPAM etc as I'm not sure I've seen an SMT processor with
> private caches. Some old papers seems to suggest that it might
> make sense for smt 8 and above.

Thanks for the hint, I'll think about whether some of the RDT / MPAM
cases can be applied here.

> Anyhow, patch is fine
> Reviewed-by: Jonathan Cameron <[e-mail]>

Thanks!

-Zhao

Patch

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e3a81bc64922..e9f755000356 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -241,9 +241,15 @@  static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info,
     uint32_t num_ids = 0;
 
     switch (share_level) {
+    case CPU_TOPOLOGY_LEVEL_THREAD:
+        num_ids = 1;
+        break;
     case CPU_TOPOLOGY_LEVEL_CORE:
         num_ids = 1 << apicid_core_offset(topo_info);
         break;
+    case CPU_TOPOLOGY_LEVEL_MODULE:
+        num_ids = 1 << apicid_module_offset(topo_info);
+        break;
     case CPU_TOPOLOGY_LEVEL_DIE:
         num_ids = 1 << apicid_die_offset(topo_info);
         break;
@@ -251,10 +257,6 @@  static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info,
         num_ids = 1 << apicid_pkg_offset(topo_info);
         break;
     default:
-        /*
-         * Currently there is no use case for THREAD and MODULE, so use
-         * assert directly to facilitate debugging.
-         */
         g_assert_not_reached();
     }