From patchwork Sun Sep 8 12:59:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13795436 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 857C5E6FE49 for ; Sun, 8 Sep 2024 12:45:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1snHGp-0008Uz-UQ; Sun, 08 Sep 2024 08:43:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1snHGn-0008Iw-9h; Sun, 08 Sep 2024 08:43:57 -0400 Received: from mgamail.intel.com ([198.175.65.15]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1snHGl-0006B4-NM; Sun, 08 Sep 2024 08:43:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725799436; x=1757335436; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mnsZhLOSkIt6OGn4y2rRLWIdhUwNFa/JuPtwCtNqbec=; b=Jxnsmv8VXeM6Cqoa5BflNvWXnkD9h5tziOFg1mYfrEgZnylA25pQjsdZ QBNkQ6RmAD1Oqp+MKYPblC6lyucMhViqQxnDHSk0hXuSPcCo/ZlUKwdcx ThKPNLdRBPKbIhr9+uM5K2J2JAWw3g5ZRVH2TPZUqD3iRde5SGLzGO4Lb qAByaNJy5r7Ef7sa1MBpkKymFs6YFQ6fy2A25LHM3JxKnNZjNzkUmOCH2 wjZYxTqSV3yScQYhWSLXkrse+K5Ri5uLdgjjnQ53j2KIDmwLavSl2vbv5 j6mYY5ZTDP/i8SOYKI8K7DM+PTJoConcy6WWBh5J9ODjluZk5QP1nNmaY Q==; X-CSE-ConnectionGUID: fOTMhnLLQTeJ/5bCfi16FQ== X-CSE-MsgGUID: TMA0hEfMRtuxu5juYlT4OA== X-IronPort-AV: E=McAfee;i="6700,10204,11189"; a="28238217" X-IronPort-AV: E=Sophos;i="6.10,212,1719903600"; d="scan'208";a="28238217" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2024 05:43:55 -0700 X-CSE-ConnectionGUID: bvTZQcDaRguVcTIRDYQTng== X-CSE-MsgGUID: KH+c+HSBRdiHXCVmCm6NkQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,212,1719903600"; d="scan'208";a="97196618" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa001.fm.intel.com with ESMTP; 08 Sep 2024 05:43:48 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH v2 5/7] i386/cpu: Support thread and module level cache topology Date: Sun, 8 Sep 2024 20:59:18 +0800 Message-Id: <20240908125920.1160236-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240908125920.1160236-1-zhao1.liu@intel.com> References: <20240908125920.1160236-1-zhao1.liu@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.15; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.145, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Allow cache to be defined at the thread and module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma --- target/i386/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e3a81bc64922..e9f755000356 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -241,9 +241,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, uint32_t num_ids = 0; switch (share_level) { + case CPU_TOPOLOGY_LEVEL_THREAD: + num_ids = 1; + break; case CPU_TOPOLOGY_LEVEL_CORE: num_ids = 1 << apicid_core_offset(topo_info); break; + case CPU_TOPOLOGY_LEVEL_MODULE: + num_ids = 1 << apicid_module_offset(topo_info); + break; case CPU_TOPOLOGY_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; @@ -251,10 +257,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, num_ids = 1 << apicid_pkg_offset(topo_info); break; default: - /* - * Currently there is no use case for THREAD and MODULE, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); }