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[176.184.54.166]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8d2583177dsm397876466b.30.2024.09.09.16.19.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 09 Sep 2024 16:19:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , qemu-s390x@nongnu.org, Thomas Huth , Ilya Leoshkevich , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH v2 06/10 4/4] target/s390x: Use deposit to set cc_op in save_link_info Date: Tue, 10 Sep 2024 01:19:10 +0200 Message-ID: <20240909231910.14428-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240605215739.4758-7-richard.henderson@linaro.org> References: <20240605215739.4758-7-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philmd@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20240605215739.4758-7-richard.henderson@linaro.org> [PMD: Split patch, part 4/4] Signed-off-by: Philippe Mathieu-Daudé --- target/s390x/tcg/translate.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index bfb7662329..b9fdfdc85a 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1433,11 +1433,13 @@ static void save_link_info(DisasContext *s, DisasOps *o) tcg_gen_shri_i64(t1, psw_mask, 16); /* Deposit pc to replace garbage bits below program mask. */ gen_psw_addr_disp(s, t2, s->ilen); - tcg_gen_deposit_i64(o->out, t1, t2, 0, 24); + tcg_gen_deposit_i64(t1, t1, t2, 0, 24); + /* + * Deposit cc to replace garbage bits above program mask. + * Note that cc is in [0-3], thus [63:30] are set to zero. + */ tcg_gen_extu_i32_i64(t2, cc_op); - tcg_gen_shli_i64(t2, t2, 28); - tcg_gen_or_i64(o->out, o->out, t2); - + tcg_gen_deposit_i64(t1, t1, t2, 28, 64 - 28); /* Install ilen. */ tcg_gen_ori_i64(t1, t1, (s->ilen / 2) << 30);