mbox

[PULL,00/47] riscv-to-apply queue

Message ID 20240912052953.2552501-1-alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show

Pull-request

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240912-1

Message

Alistair Francis Sept. 12, 2024, 5:29 a.m. UTC 
The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:

  Merge tag 'pull-testing-gdbstub-oct-100924-1' of https://gitlab.com/stsquad/qemu into staging (2024-09-11 13:17:29 +0100)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240912-1

for you to fetch changes up to 90d5d3c1115399d8e27621efd69dfa74a35a4932:

  hw/intc: riscv-imsic: Fix interrupt state updates. (2024-09-12 15:05:10 +1000)

----------------------------------------------------------------
RISC-V PR for 9.2

* Add a property to set vl to ceil(AVL/2)
* Enable numamem testing for RISC-V
* Consider MISA bit choice in implied rule
* Fix the za64rs priv spec requirements
* Enable Bit Manip for OpenTitan Ibex CPU
* Fix the group bit setting of AIA with KVM
* Stop timer with infinite timecmp
* Add 'fcsr' register to QEMU log as a part of F extension
* Fix riscv64 build on musl libc
* Add preliminary textra trigger CSR functions
* RISC-V IOMMU support
* RISC-V bsd-user support
* Respect firmware ELF entry point
* Add Svvptc extension support
* Fix masking of rv32 physical address
* Fix linking problem with semihosting disabled
* Fix IMSIC interrupt state updates

----------------------------------------------------------------
Alexandre Ghiti (1):
      target: riscv: Add Svvptc extension support

Alistair Francis (1):
      target: riscv: Enable Bit Manip for OpenTitan Ibex CPU

Alvin Chang (2):
      target/riscv: Preliminary textra trigger CSR writting support
      target/riscv: Add textra matching condition for the triggers

Andrew Jones (3):
      target/riscv/kvm: Fix the group bit setting of AIA
      target/riscv: Stop timer with infinite timecmp
      target/riscv32: Fix masking of physical address

Daniel Henrique Barboza (5):
      target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule
      pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
      test/qtest: add riscv-iommu-pci tests
      qtest/riscv-iommu-test: add init queues test
      docs/specs: add riscv-iommu

Haibo Xu (3):
      tests/acpi: Add empty ACPI SRAT data file for RISC-V
      tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V
      tests/acpi: Add expected ACPI SRAT AML file for RISC-V

Jason Chien (1):
      target/riscv: Add a property to set vl to ceil(AVL/2)

Maria Klauchek (1):
      target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension

Mark Corbin (15):
      bsd-user: Implement RISC-V CPU initialization and main loop
      bsd-user: Add RISC-V CPU execution loop and syscall handling
      bsd-user: Implement RISC-V CPU register cloning and reset functions
      bsd-user: Implement RISC-V TLS register setup
      bsd-user: Add RISC-V ELF definitions and hardware capability detection
      bsd-user: Define RISC-V register structures and register copying
      bsd-user: Add RISC-V signal trampoline setup function
      bsd-user: Implement RISC-V sysarch system call emulation
      bsd-user: Add RISC-V thread setup and initialization support
      bsd-user: Define RISC-V VM parameters and helper functions
      bsd-user: Define RISC-V system call structures and constants
      bsd-user: Define RISC-V signal handling structures and constants
      bsd-user: Implement RISC-V signal trampoline setup functions
      bsd-user: Implement 'get_mcontext' for RISC-V
      bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

Milan P. Stanić (1):
      util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc

Samuel Holland (1):
      hw/riscv: Respect firmware ELF entry point

Thomas Huth (1):
      target/riscv/cpu_helper: Fix linking problem with semihosting disabled

Tomasz Jeznach (9):
      exec/memtxattr: add process identifier to the transaction attributes
      hw/riscv: add riscv-iommu-bits.h
      hw/riscv: add RISC-V IOMMU base emulation
      hw/riscv: add riscv-iommu-pci reference device
      hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
      hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
      hw/riscv/riscv-iommu: add ATS support
      hw/riscv/riscv-iommu: add DBG support
      hw/intc: riscv-imsic: Fix interrupt state updates.

Vladimir Isaev (1):
      target/riscv: fix za64rs enabling

Warner Losh (2):
      bsd-user: Add generic RISC-V64 target definitions
      bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

 docs/specs/index.rst                      |    1 +
 docs/specs/pci-ids.rst                    |    2 +
 docs/specs/riscv-iommu.rst                |   90 ++
 docs/system/riscv/virt.rst                |   13 +
 configs/targets/riscv64-bsd-user.mak      |    4 +
 meson.build                               |    1 +
 bsd-user/riscv/target.h                   |   20 +
 bsd-user/riscv/target_arch.h              |   27 +
 bsd-user/riscv/target_arch_cpu.h          |  147 ++
 bsd-user/riscv/target_arch_elf.h          |   42 +
 bsd-user/riscv/target_arch_reg.h          |   88 ++
 bsd-user/riscv/target_arch_signal.h       |   75 +
 bsd-user/riscv/target_arch_sigtramp.h     |   42 +
 bsd-user/riscv/target_arch_sysarch.h      |   41 +
 bsd-user/riscv/target_arch_thread.h       |   47 +
 bsd-user/riscv/target_arch_vmparam.h      |   53 +
 bsd-user/riscv/target_syscall.h           |   38 +
 hw/riscv/riscv-iommu-bits.h               |  421 +++++
 hw/riscv/riscv-iommu.h                    |  149 ++
 hw/riscv/trace.h                          |    1 +
 include/exec/memattrs.h                   |    5 +
 include/hw/pci/pci.h                      |    1 +
 include/hw/riscv/boot.h                   |    4 +-
 include/hw/riscv/iommu.h                  |   36 +
 target/riscv/cpu_bits.h                   |   10 +
 target/riscv/cpu_cfg.h                    |    2 +
 target/riscv/debug.h                      |    3 +
 tests/qtest/libqos/riscv-iommu.h          |  101 ++
 bsd-user/riscv/signal.c                   |  170 ++
 bsd-user/riscv/target_arch_cpu.c          |   29 +
 hw/intc/riscv_imsic.c                     |   50 +-
 hw/riscv/boot.c                           |   11 +-
 hw/riscv/microchip_pfsoc.c                |    2 +-
 hw/riscv/opentitan.c                      |    3 +-
 hw/riscv/riscv-iommu-pci.c                |  202 +++
 hw/riscv/riscv-iommu.c                    | 2431 +++++++++++++++++++++++++++++
 hw/riscv/shakti_c.c                       |   13 +-
 hw/riscv/sifive_u.c                       |    4 +-
 hw/riscv/spike.c                          |    5 +-
 hw/riscv/virt.c                           |   37 +-
 target/riscv/cpu.c                        |   16 +-
 target/riscv/cpu_helper.c                 |    8 +-
 target/riscv/debug.c                      |  114 +-
 target/riscv/kvm/kvm-cpu.c                |    4 +-
 target/riscv/tcg/tcg-cpu.c                |   13 +-
 target/riscv/time_helper.c                |    1 +
 target/riscv/vector_helper.c              |    2 +
 tests/qtest/bios-tables-test.c            |   28 +
 tests/qtest/libqos/riscv-iommu.c          |   76 +
 tests/qtest/riscv-iommu-test.c            |  220 +++
 util/cpuinfo-riscv.c                      |    1 +
 hw/riscv/Kconfig                          |    4 +
 hw/riscv/meson.build                      |    1 +
 hw/riscv/trace-events                     |   17 +
 target/riscv/Kconfig                      |    4 +-
 tests/data/acpi/riscv64/virt/SRAT.numamem |  Bin 0 -> 108 bytes
 tests/qtest/libqos/meson.build            |    4 +
 tests/qtest/meson.build                   |    1 +
 58 files changed, 4877 insertions(+), 58 deletions(-)
 create mode 100644 docs/specs/riscv-iommu.rst
 create mode 100644 configs/targets/riscv64-bsd-user.mak
 create mode 100644 bsd-user/riscv/target.h
 create mode 100644 bsd-user/riscv/target_arch.h
 create mode 100644 bsd-user/riscv/target_arch_cpu.h
 create mode 100644 bsd-user/riscv/target_arch_elf.h
 create mode 100644 bsd-user/riscv/target_arch_reg.h
 create mode 100644 bsd-user/riscv/target_arch_signal.h
 create mode 100644 bsd-user/riscv/target_arch_sigtramp.h
 create mode 100644 bsd-user/riscv/target_arch_sysarch.h
 create mode 100644 bsd-user/riscv/target_arch_thread.h
 create mode 100644 bsd-user/riscv/target_arch_vmparam.h
 create mode 100644 bsd-user/riscv/target_syscall.h
 create mode 100644 hw/riscv/riscv-iommu-bits.h
 create mode 100644 hw/riscv/riscv-iommu.h
 create mode 100644 hw/riscv/trace.h
 create mode 100644 include/hw/riscv/iommu.h
 create mode 100644 tests/qtest/libqos/riscv-iommu.h
 create mode 100644 bsd-user/riscv/signal.c
 create mode 100644 bsd-user/riscv/target_arch_cpu.c
 create mode 100644 hw/riscv/riscv-iommu-pci.c
 create mode 100644 hw/riscv/riscv-iommu.c
 create mode 100644 tests/qtest/libqos/riscv-iommu.c
 create mode 100644 tests/qtest/riscv-iommu-test.c
 create mode 100644 hw/riscv/trace-events
 create mode 100644 tests/data/acpi/riscv64/virt/SRAT.numamem

Comments

Peter Maydell Sept. 13, 2024, 10:37 a.m. UTC | #1 
On Thu, 12 Sept 2024 at 06:30, Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
>
>   Merge tag 'pull-testing-gdbstub-oct-100924-1' of https://gitlab.com/stsquad/qemu into staging (2024-09-11 13:17:29 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240912-1
>
> for you to fetch changes up to 90d5d3c1115399d8e27621efd69dfa74a35a4932:
>
>   hw/intc: riscv-imsic: Fix interrupt state updates. (2024-09-12 15:05:10 +1000)
>
> ----------------------------------------------------------------
> RISC-V PR for 9.2
>
> * Add a property to set vl to ceil(AVL/2)
> * Enable numamem testing for RISC-V
> * Consider MISA bit choice in implied rule
> * Fix the za64rs priv spec requirements
> * Enable Bit Manip for OpenTitan Ibex CPU
> * Fix the group bit setting of AIA with KVM
> * Stop timer with infinite timecmp
> * Add 'fcsr' register to QEMU log as a part of F extension
> * Fix riscv64 build on musl libc
> * Add preliminary textra trigger CSR functions
> * RISC-V IOMMU support
> * RISC-V bsd-user support
> * Respect firmware ELF entry point
> * Add Svvptc extension support
> * Fix masking of rv32 physical address
> * Fix linking problem with semihosting disabled
> * Fix IMSIC interrupt state updates

Hi; this fails to build on FreeBSD:

https://gitlab.com/qemu-project/qemu/-/jobs/7817823771

In file included from ../bsd-user/elfload.c:31:
In file included from ../bsd-user/freebsd/target_os_stack.h:24:
../bsd-user/riscv/target_arch_sigtramp.h:32:33: error: initializer
element is not a compile-time constant
32 | /*2*/ const_le32(0x00050513 + (sigf_uc << 20)), /*addi a0,a0,sigf_uc*/
   |                  ~~~~~~~~~~~^~~~~~~~~~~~~~~~~
/tmp/cirrus-ci-build/include/qemu/bswap.h:168:26: note: expanded from
macro 'const_le32'
168 | # define const_le32(_x) (_x)
    |                          ^~


and

In file included from ../bsd-user/main.c:53:
../bsd-user/riscv/target_arch_cpu.h:126:13: error: call to undeclared
function 'force_sig_fault'; ISO C99 and later do not support implicit
function declarations [-Werror,-Wimplicit-function-declaration]
126 | force_sig_fault(signo, code, env->pc);
    | ^
../bsd-user/riscv/target_arch_cpu.h:129:9: error: call to undeclared
function 'process_pending_signals'; ISO C99 and later do not support
implicit function declarations
[-Werror,-Wimplicit-function-declaration]
129 | process_pending_signals(env);
    | ^
../bsd-user/main.c:608:5: error: call to undeclared function
'signal_init'; ISO C99 and later do not support implicit function
declarations [-Werror,-Wimplicit-function-declaration]
608 | signal_init();
    | ^
3 errors generated.

thanks
-- PMM
Alistair Francis Sept. 14, 2024, 9:15 a.m. UTC | #2 
On Fri, Sep 13, 2024 at 8:37 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Thu, 12 Sept 2024 at 06:30, Alistair Francis <alistair23@gmail.com> wrote:
> >
> > The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
> >
> >   Merge tag 'pull-testing-gdbstub-oct-100924-1' of https://gitlab.com/stsquad/qemu into staging (2024-09-11 13:17:29 +0100)
> >
> > are available in the Git repository at:
> >
> >   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240912-1
> >
> > for you to fetch changes up to 90d5d3c1115399d8e27621efd69dfa74a35a4932:
> >
> >   hw/intc: riscv-imsic: Fix interrupt state updates. (2024-09-12 15:05:10 +1000)
> >
> > ----------------------------------------------------------------
> > RISC-V PR for 9.2
> >
> > * Add a property to set vl to ceil(AVL/2)
> > * Enable numamem testing for RISC-V
> > * Consider MISA bit choice in implied rule
> > * Fix the za64rs priv spec requirements
> > * Enable Bit Manip for OpenTitan Ibex CPU
> > * Fix the group bit setting of AIA with KVM
> > * Stop timer with infinite timecmp
> > * Add 'fcsr' register to QEMU log as a part of F extension
> > * Fix riscv64 build on musl libc
> > * Add preliminary textra trigger CSR functions
> > * RISC-V IOMMU support
> > * RISC-V bsd-user support
> > * Respect firmware ELF entry point
> > * Add Svvptc extension support
> > * Fix masking of rv32 physical address
> > * Fix linking problem with semihosting disabled
> > * Fix IMSIC interrupt state updates
>
> Hi; this fails to build on FreeBSD:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/7817823771

Ajeet do you mind looking at this failure and sending a new series with a fix

Alistair

>
> In file included from ../bsd-user/elfload.c:31:
> In file included from ../bsd-user/freebsd/target_os_stack.h:24:
> ../bsd-user/riscv/target_arch_sigtramp.h:32:33: error: initializer
> element is not a compile-time constant
> 32 | /*2*/ const_le32(0x00050513 + (sigf_uc << 20)), /*addi a0,a0,sigf_uc*/
>    |                  ~~~~~~~~~~~^~~~~~~~~~~~~~~~~
> /tmp/cirrus-ci-build/include/qemu/bswap.h:168:26: note: expanded from
> macro 'const_le32'
> 168 | # define const_le32(_x) (_x)
>     |                          ^~
>
>
> and
>
> In file included from ../bsd-user/main.c:53:
> ../bsd-user/riscv/target_arch_cpu.h:126:13: error: call to undeclared
> function 'force_sig_fault'; ISO C99 and later do not support implicit
> function declarations [-Werror,-Wimplicit-function-declaration]
> 126 | force_sig_fault(signo, code, env->pc);
>     | ^
> ../bsd-user/riscv/target_arch_cpu.h:129:9: error: call to undeclared
> function 'process_pending_signals'; ISO C99 and later do not support
> implicit function declarations
> [-Werror,-Wimplicit-function-declaration]
> 129 | process_pending_signals(env);
>     | ^
> ../bsd-user/main.c:608:5: error: call to undeclared function
> 'signal_init'; ISO C99 and later do not support implicit function
> declarations [-Werror,-Wimplicit-function-declaration]
> 608 | signal_init();
>     | ^
> 3 errors generated.
>
> thanks
> -- PMM
Daniel Henrique Barboza Sept. 15, 2024, 7:58 p.m. UTC | #3 
Hi Peter, Alistair,

On 9/14/24 6:15 AM, Alistair Francis wrote:
> On Fri, Sep 13, 2024 at 8:37 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>>
>> On Thu, 12 Sept 2024 at 06:30, Alistair Francis <alistair23@gmail.com> wrote:
>>>
>>> The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
>>>
>>>    Merge tag 'pull-testing-gdbstub-oct-100924-1' of https://gitlab.com/stsquad/qemu into staging (2024-09-11 13:17:29 +0100)
>>>
>>> are available in the Git repository at:
>>>
>>>    https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240912-1
>>>
>>> for you to fetch changes up to 90d5d3c1115399d8e27621efd69dfa74a35a4932:
>>>
>>>    hw/intc: riscv-imsic: Fix interrupt state updates. (2024-09-12 15:05:10 +1000)
>>>
>>> ----------------------------------------------------------------
>>> RISC-V PR for 9.2
>>>
>>> * Add a property to set vl to ceil(AVL/2)
>>> * Enable numamem testing for RISC-V
>>> * Consider MISA bit choice in implied rule
>>> * Fix the za64rs priv spec requirements
>>> * Enable Bit Manip for OpenTitan Ibex CPU
>>> * Fix the group bit setting of AIA with KVM
>>> * Stop timer with infinite timecmp
>>> * Add 'fcsr' register to QEMU log as a part of F extension
>>> * Fix riscv64 build on musl libc
>>> * Add preliminary textra trigger CSR functions
>>> * RISC-V IOMMU support
>>> * RISC-V bsd-user support
>>> * Respect firmware ELF entry point
>>> * Add Svvptc extension support
>>> * Fix masking of rv32 physical address
>>> * Fix linking problem with semihosting disabled
>>> * Fix IMSIC interrupt state updates
>>
>> Hi; this fails to build on FreeBSD:
>>
>> https://gitlab.com/qemu-project/qemu/-/jobs/7817823771

Is this one of those jobs that are only available when running the main pipeline? I don't
have this x86-freebsd runner when triggering the gitlab pipeline. I ended up installing a
FreeBSD VM and using it to reproduce the problem.

Would be nice to have access to a FreeBSD runner as a regular user, even if just for x86_64,
to help detect these build problems before sending a PR.


> 
> Ajeet do you mind looking at this failure and sending a new series with a fix


I sent some build fixes in patches 27 and 32 that worked for me. Since they are trivial I think
you could just squash them in the PR and send a v2.



Thanks,

Daniel

> 
> Alistair
> 
>>
>> In file included from ../bsd-user/elfload.c:31:
>> In file included from ../bsd-user/freebsd/target_os_stack.h:24:
>> ../bsd-user/riscv/target_arch_sigtramp.h:32:33: error: initializer
>> element is not a compile-time constant
>> 32 | /*2*/ const_le32(0x00050513 + (sigf_uc << 20)), /*addi a0,a0,sigf_uc*/
>>     |                  ~~~~~~~~~~~^~~~~~~~~~~~~~~~~
>> /tmp/cirrus-ci-build/include/qemu/bswap.h:168:26: note: expanded from
>> macro 'const_le32'
>> 168 | # define const_le32(_x) (_x)
>>      |                          ^~
>>
>>
>> and
>>
>> In file included from ../bsd-user/main.c:53:
>> ../bsd-user/riscv/target_arch_cpu.h:126:13: error: call to undeclared
>> function 'force_sig_fault'; ISO C99 and later do not support implicit
>> function declarations [-Werror,-Wimplicit-function-declaration]
>> 126 | force_sig_fault(signo, code, env->pc);
>>      | ^
>> ../bsd-user/riscv/target_arch_cpu.h:129:9: error: call to undeclared
>> function 'process_pending_signals'; ISO C99 and later do not support
>> implicit function declarations
>> [-Werror,-Wimplicit-function-declaration]
>> 129 | process_pending_signals(env);
>>      | ^
>> ../bsd-user/main.c:608:5: error: call to undeclared function
>> 'signal_init'; ISO C99 and later do not support implicit function
>> declarations [-Werror,-Wimplicit-function-declaration]
>> 608 | signal_init();
>>      | ^
>> 3 errors generated.
>>
>> thanks
>> -- PMM
>
Thomas Huth Sept. 16, 2024, 6:12 a.m. UTC | #4 
On 15/09/2024 21.58, Daniel Henrique Barboza wrote:
> Hi Peter, Alistair,
> 
> On 9/14/24 6:15 AM, Alistair Francis wrote:
>> On Fri, Sep 13, 2024 at 8:37 PM Peter Maydell <peter.maydell@linaro.org> 
>> wrote:
>>>
>>> On Thu, 12 Sept 2024 at 06:30, Alistair Francis <alistair23@gmail.com> 
>>> wrote:
>>>>
>>>> The following changes since commit 
>>>> a4eb31c678400472de0b4915b9154a7c20d8332f:
>>>>
>>>>    Merge tag 'pull-testing-gdbstub-oct-100924-1' of https://gitlab.com/ 
>>>> stsquad/qemu into staging (2024-09-11 13:17:29 +0100)
>>>>
>>>> are available in the Git repository at:
>>>>
>>>>    https://github.com/alistair23/qemu.git tags/pull-riscv-to- 
>>>> apply-20240912-1
>>>>
>>>> for you to fetch changes up to 90d5d3c1115399d8e27621efd69dfa74a35a4932:
>>>>
>>>>    hw/intc: riscv-imsic: Fix interrupt state updates. (2024-09-12 
>>>> 15:05:10 +1000)
>>>>
>>>> ----------------------------------------------------------------
>>>> RISC-V PR for 9.2
>>>>
>>>> * Add a property to set vl to ceil(AVL/2)
>>>> * Enable numamem testing for RISC-V
>>>> * Consider MISA bit choice in implied rule
>>>> * Fix the za64rs priv spec requirements
>>>> * Enable Bit Manip for OpenTitan Ibex CPU
>>>> * Fix the group bit setting of AIA with KVM
>>>> * Stop timer with infinite timecmp
>>>> * Add 'fcsr' register to QEMU log as a part of F extension
>>>> * Fix riscv64 build on musl libc
>>>> * Add preliminary textra trigger CSR functions
>>>> * RISC-V IOMMU support
>>>> * RISC-V bsd-user support
>>>> * Respect firmware ELF entry point
>>>> * Add Svvptc extension support
>>>> * Fix masking of rv32 physical address
>>>> * Fix linking problem with semihosting disabled
>>>> * Fix IMSIC interrupt state updates
>>>
>>> Hi; this fails to build on FreeBSD:
>>>
>>> https://gitlab.com/qemu-project/qemu/-/jobs/7817823771
> 
> Is this one of those jobs that are only available when running the main 
> pipeline? I don't
> have this x86-freebsd runner when triggering the gitlab pipeline. I ended up 
> installing a
> FreeBSD VM and using it to reproduce the problem.
> 
> Would be nice to have access to a FreeBSD runner as a regular user, even if 
> just for x86_64,
> to help detect these build problems before sending a PR.

You can enable this job for your pipelines, too, see 
.gitlab-ci.d/cirrus/README.rst for information how to configure it.

If you have a Linux host with KVM, you could alternatively also use "make 
vm-build-freebsd" on your local machine instead.

  Thomas
Daniel Henrique Barboza Sept. 16, 2024, 10:43 a.m. UTC | #5 
On 9/16/24 3:12 AM, Thomas Huth wrote:
> On 15/09/2024 21.58, Daniel Henrique Barboza wrote:
>> Hi Peter, Alistair,
>>
>> On 9/14/24 6:15 AM, Alistair Francis wrote:
>>> On Fri, Sep 13, 2024 at 8:37 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>>>>
>>>> On Thu, 12 Sept 2024 at 06:30, Alistair Francis <alistair23@gmail.com> wrote:
>>>>>
>>>>> The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
>>>>>
>>>>>    Merge tag 'pull-testing-gdbstub-oct-100924-1' of https://gitlab.com/ stsquad/qemu into staging (2024-09-11 13:17:29 +0100)
>>>>>
>>>>> are available in the Git repository at:
>>>>>
>>>>>    https://github.com/alistair23/qemu.git tags/pull-riscv-to- apply-20240912-1
>>>>>
>>>>> for you to fetch changes up to 90d5d3c1115399d8e27621efd69dfa74a35a4932:
>>>>>
>>>>>    hw/intc: riscv-imsic: Fix interrupt state updates. (2024-09-12 15:05:10 +1000)
>>>>>
>>>>> ----------------------------------------------------------------
>>>>> RISC-V PR for 9.2
>>>>>
>>>>> * Add a property to set vl to ceil(AVL/2)
>>>>> * Enable numamem testing for RISC-V
>>>>> * Consider MISA bit choice in implied rule
>>>>> * Fix the za64rs priv spec requirements
>>>>> * Enable Bit Manip for OpenTitan Ibex CPU
>>>>> * Fix the group bit setting of AIA with KVM
>>>>> * Stop timer with infinite timecmp
>>>>> * Add 'fcsr' register to QEMU log as a part of F extension
>>>>> * Fix riscv64 build on musl libc
>>>>> * Add preliminary textra trigger CSR functions
>>>>> * RISC-V IOMMU support
>>>>> * RISC-V bsd-user support
>>>>> * Respect firmware ELF entry point
>>>>> * Add Svvptc extension support
>>>>> * Fix masking of rv32 physical address
>>>>> * Fix linking problem with semihosting disabled
>>>>> * Fix IMSIC interrupt state updates
>>>>
>>>> Hi; this fails to build on FreeBSD:
>>>>
>>>> https://gitlab.com/qemu-project/qemu/-/jobs/7817823771
>>
>> Is this one of those jobs that are only available when running the main pipeline? I don't
>> have this x86-freebsd runner when triggering the gitlab pipeline. I ended up installing a
>> FreeBSD VM and using it to reproduce the problem.
>>
>> Would be nice to have access to a FreeBSD runner as a regular user, even if just for x86_64,
>> to help detect these build problems before sending a PR.
> 
> You can enable this job for your pipelines, too, see .gitlab-ci.d/cirrus/README.rst for information how to configure it.

Nice! Thanks!

> 
> If you have a Linux host with KVM, you could alternatively also use "make vm-build-freebsd" on your local machine instead.


Way easier than what I did :D next time I'll grep the docs.


Daniel

> 
>   Thomas
>