Message ID | 20240912052953.2552501-47-alistair.francis@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71908fc8fdesm3833034b3a.1.2024.09.11.22.32.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:32:26 -0700 (PDT) From: Alistair Francis <alistair23@gmail.com> X-Google-Original-From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Thomas Huth <thuth@redhat.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 46/47] target/riscv/cpu_helper: Fix linking problem with semihosting disabled Date: Thu, 12 Sep 2024 15:29:51 +1000 Message-ID: <20240912052953.2552501-47-alistair.francis@wdc.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240912052953.2552501-1-alistair.francis@wdc.com> References: <20240912052953.2552501-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org |
Series |
[PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2)
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diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4b2c72780c..a935377b4a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1674,10 +1674,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { +#ifdef CONFIG_TCG case RISCV_EXCP_SEMIHOST: do_common_semihosting(cs); env->pc += 4; return; +#endif case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig index c332616d36..11bc09b414 100644 --- a/target/riscv/Kconfig +++ b/target/riscv/Kconfig @@ -1,9 +1,9 @@ config RISCV32 bool - imply ARM_COMPATIBLE_SEMIHOSTING if TCG + select ARM_COMPATIBLE_SEMIHOSTING if TCG select DEVICE_TREE # needed by boot.c config RISCV64 bool - imply ARM_COMPATIBLE_SEMIHOSTING if TCG + select ARM_COMPATIBLE_SEMIHOSTING if TCG select DEVICE_TREE # needed by boot.c