From patchwork Thu Sep 19 06:11:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13807426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBC5ACE8D49 for ; Thu, 19 Sep 2024 06:00:27 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1srAA6-0003W3-Bm; Thu, 19 Sep 2024 01:57:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1srA9q-0002pw-M6; Thu, 19 Sep 2024 01:56:50 -0400 Received: from mgamail.intel.com ([192.198.163.15]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1srA9o-0007Qp-Ij; Thu, 19 Sep 2024 01:56:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726725409; x=1758261409; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cQ08ivvbyToxE/NhN3+dCAQERQMlDYEq9vSrgiTrea4=; b=SwTwys4lQdupoEm7YRdBLe6RnhtPjAoysi8gt1QBkmwXZ5D//FRnup/8 GOVs6UQm8yMcRQlYuZfKFQU4evY/AOsB0tx/fB0KnkHDAIHpxly2pv9ST 9sSjhGy32LGAIT8/lOVYovtPRc6dUIaKQ6pb25WfSR8Q7/n3e6QQ0YG8w MoWqh7ikvV+ARBasRc3tHmzKvv1P+Ihuy3llydZn97ix/xDpHJtNYqZqT aN/+5G+F0Ql59upV8b1JVNDXE9vvppLpg6Cl4s+i9wo/Pf9lp0+h3gqiz +AYZ340cubu5uLgyXa3jv6eVmmWTCXrht8dQOJVBF55TStN+K9OaZry83 g==; X-CSE-ConnectionGUID: LIgm+4apTEy/qJYAFUTzxg== X-CSE-MsgGUID: xcgCJtXaQ0CbgrWQql+EbA== X-IronPort-AV: E=McAfee;i="6700,10204,11199"; a="25813797" X-IronPort-AV: E=Sophos;i="6.10,240,1719903600"; d="scan'208";a="25813797" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2024 22:56:47 -0700 X-CSE-ConnectionGUID: rMNYl1sATnOo2bqgjGFlQw== X-CSE-MsgGUID: V3LeJGc2RIC+vnG1nDqGFA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,240,1719903600"; d="scan'208";a="69418845" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa006.fm.intel.com with ESMTP; 18 Sep 2024 22:56:41 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Sergio Lopez , Jason Wang , Stefano Stabellini , Anthony PERARD , Paul Durrant , "Edgar E . Iglesias" , Eric Blake , Markus Armbruster , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC v2 12/12] i386: Support custom topology for microvm, pc-i440fx and pc-q35 Date: Thu, 19 Sep 2024 14:11:28 +0800 Message-Id: <20240919061128.769139-13-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240919061128.769139-1-zhao1.liu@intel.com> References: <20240919061128.769139-1-zhao1.liu@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.198.163.15; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org With custom topology enabling, user could configure hyrid CPU topology from CLI. For example, create a Intel Core (P core) with 2 threads and 2 Intel Atom (E core) with single thread for PC machine: -smp maxsockets=1,maxdies=1,maxmodules=2,maxcores=2,maxthreads=2 -machine pc,custom-topo=on \ -device cpu-socket,id=sock0 \ -device cpu-die,id=die0,bus=sock0 \ -device cpu-module,id=mod0,bus=die0 \ -device cpu-module,id=mod1,bus=die0 \ -device x86-intel-core,id=core0,bus=mod0 \ -device x86-intel-atom,id=core1,bus=mod1 \ -device x86-intel-atom,id=core2,bus=mod1 \ -device host-x86_64-cpu,id=cpu0,socket-id=0,die-id=0,module-id=0,core-id=0,thread-id=0 \ -device host-x86_64-cpu,id=cpu1,socket-id=0,die-id=0,module-id=0,core-id=0,thread-id=1 \ -device host-x86_64-cpu,id=cpu2,socket-id=0,die-id=0,module-id=1,core-id=0,thread-id=0 \ -device host-x86_64-cpu,id=cpu3,socket-id=0,die-id=0,module-id=1,core-id=1,thread-id=0 Signed-off-by: Zhao Liu --- hw/i386/microvm.c | 1 + hw/i386/pc_piix.c | 1 + hw/i386/pc_q35.c | 1 + hw/i386/x86-common.c | 6 ++++++ 4 files changed, 9 insertions(+) diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index dc9b21a34230..bd03b6946e6c 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -671,6 +671,7 @@ static void microvm_class_init(ObjectClass *oc, void *data) mc->reset = microvm_machine_reset; mc->post_init = microvm_machine_state_post_init; + mc->smp_props.custom_topo_supported = true; /* hotplug (for cpu coldplug) */ mc->get_hotplug_handler = microvm_get_hotplug_handler; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index c1db2f3129cf..9c696a226858 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -473,6 +473,7 @@ static void pc_i440fx_machine_options(MachineClass *m) m->no_floppy = !module_object_class_by_name(TYPE_ISA_FDC); m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); m->post_init = pc_post_init1; + m->smp_props.custom_topo_supported = true; machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 9ce3e65d7182..9241366ff351 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -356,6 +356,7 @@ static void pc_q35_machine_options(MachineClass *m) m->max_cpus = 4096; m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); m->post_init = pc_q35_post_init; + m->smp_props.custom_topo_supported = true; machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 58591e015569..2995eed5d670 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -195,6 +195,12 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version) } possible_cpus = mc->possible_cpu_arch_ids(ms); + + /* Leave user to add CPUs. */ + if (ms->topo->custom_topo_enabled) { + return; + } + for (i = 0; i < ms->smp.cpus; i++) { x86_cpu_new(x86ms, i, possible_cpus->cpus[i].arch_id, &error_fatal); }