@@ -82,6 +82,9 @@ config IMX
select SSI
select USB_EHCI_SYSBUS
+config STM32_RCC
+ bool
+
config STM32F2XX_SYSCFG
bool
@@ -106,6 +106,7 @@ system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
system_ss.add(when: 'CONFIG_XLNX_VERSAL_TRNG', if_true: files(
'xlnx-versal-trng.c',
))
+system_ss.add(when: 'CONFIG_STM32_RCC', if_true: files('stm32_rcc.c'))
system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))
system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
system_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c'))
new file mode 100644
@@ -0,0 +1,162 @@
+/*
+ * STM32 RCC (only reset and enable registers are implemented)
+ *
+ * Copyright (c) 2024 Román Cárdenas <rcardenas.rod@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "hw/irq.h"
+#include "migration/vmstate.h"
+#include "hw/misc/stm32_rcc.h"
+
+static void stm32_rcc_reset(DeviceState *dev)
+{
+ STM32RccState *s = STM32_RCC(dev);
+
+ for (int i = 0; i < STM32_RCC_NREGS; i++) {
+ s->regs[i] = 0;
+ }
+}
+
+static uint64_t stm32_rcc_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ STM32RccState *s = STM32_RCC(opaque);
+
+ uint32_t value = 0;
+ if (addr > STM32_RCC_DCKCFGR2) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
+ __func__, addr);
+ } else {
+ value = s->regs[addr >> 2];
+ }
+ trace_stm32_rcc_read(addr, value);
+ return value;
+}
+
+static void stm32_rcc_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ STM32RccState *s = STM32_RCC(opaque);
+ uint32_t value = val64;
+ uint32_t prev_value, new_value, irq_offset;
+
+ trace_stm32_rcc_write(value, addr);
+
+ if (addr > STM32_RCC_DCKCFGR2) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
+ __func__, addr);
+ return;
+ }
+
+ switch (addr) {
+ case STM32_RCC_AHB1_RSTR...STM32_RCC_APB2_RSTR:
+ prev_value = s->regs[addr / 4];
+ s->regs[addr / 4] = value;
+
+ irq_offset = ((addr - STM32_RCC_AHB1_RSTR) / 4) * 32;
+ for (int i = 0; i < 32; i++) {
+ new_value = extract32(value, i, 1);
+ if (extract32(prev_value, i, 1) && !new_value) {
+ trace_stm32_rcc_pulse_reset(irq_offset + i, new_value);
+ qemu_set_irq(s->reset_irq[irq_offset + i], new_value);
+ }
+ }
+ return;
+ case STM32_RCC_AHB1_ENR...STM32_RCC_APB2_ENR:
+ prev_value = s->regs[addr / 4];
+ s->regs[addr / 4] = value;
+
+ irq_offset = ((addr - STM32_RCC_AHB1_ENR) / 4) * 32;
+ for (int i = 0; i < 32; i++) {
+ new_value = extract32(value, i, 1);
+ if (!extract32(prev_value, i, 1) && new_value) {
+ trace_stm32_rcc_pulse_enable(irq_offset + i, new_value);
+ qemu_set_irq(s->enable_irq[irq_offset + i], new_value);
+ }
+ }
+ return;
+ default:
+ qemu_log_mask(
+ LOG_UNIMP,
+ "%s: The RCC peripheral only supports enable and reset in QEMU\n",
+ __func__
+ );
+ s->regs[addr >> 2] = value;
+ }
+}
+
+static const MemoryRegionOps stm32_rcc_ops = {
+ .read = stm32_rcc_read,
+ .write = stm32_rcc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void stm32_rcc_init(Object *obj)
+{
+ STM32RccState *s = STM32_RCC(obj);
+
+ memory_region_init_io(&s->mmio, obj, &stm32_rcc_ops, s,
+ TYPE_STM32_RCC, STM32_RCC_PERIPHERAL_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+ qdev_init_gpio_out(DEVICE(obj), s->reset_irq, STM32_RCC_NIRQS);
+ qdev_init_gpio_out(DEVICE(obj), s->enable_irq, STM32_RCC_NIRQS);
+
+ for (int i = 0; i < STM32_RCC_NIRQS; i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->reset_irq[i]);
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->enable_irq[i]);
+ }
+}
+
+static const VMStateDescription vmstate_stm32_rcc = {
+ .name = TYPE_STM32_RCC,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (const VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, STM32RccState, STM32_RCC_NREGS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void stm32_rcc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_stm32_rcc;
+ device_class_set_legacy_reset(dc, stm32_rcc_reset);
+}
+
+static const TypeInfo stm32_rcc_info = {
+ .name = TYPE_STM32_RCC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32RccState),
+ .instance_init = stm32_rcc_init,
+ .class_init = stm32_rcc_class_init,
+};
+
+static void stm32_rcc_register_types(void)
+{
+ type_register_static(&stm32_rcc_info);
+}
+
+type_init(stm32_rcc_register_types)
@@ -156,6 +156,12 @@ npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0
npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
+# stm32_rcc.c
+stm32_rcc_read(uint64_t addr, uint64_t data) "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
+stm32_rcc_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
+stm32_rcc_pulse_enable(int line, int level) "Enable: %d to %d"
+stm32_rcc_pulse_reset(int line, int level) "Reset: %d to %d"
+
# stm32f4xx_syscfg.c
stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interrupt: GPIO: %d, Line: %d; Level: %d"
stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
new file mode 100644
@@ -0,0 +1,91 @@
+/*
+ * STM32 RCC (only reset and enable registers are implemented)
+ *
+ * Copyright (c) 2024 Román Cárdenas <rcardenas.rod@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM32_RCC_H
+#define HW_STM32_RCC_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define STM32_RCC_CR 0x00
+#define STM32_RCC_PLL_CFGR 0x04
+#define STM32_RCC_CFGR 0x08
+#define STM32_RCC_CIR 0x0C
+#define STM32_RCC_AHB1_RSTR 0x10
+#define STM32_RCC_AHB2_RSTR 0x14
+#define STM32_RCC_AHB3_RSTR 0x18
+
+#define STM32_RCC_APB1_RSTR 0x20
+#define STM32_RCC_APB2_RSTR 0x24
+
+#define STM32_RCC_AHB1_ENR 0x30
+#define STM32_RCC_AHB2_ENR 0x34
+#define STM32_RCC_AHB3_ENR 0x38
+
+#define STM32_RCC_APB1_ENR 0x40
+#define STM32_RCC_APB2_ENR 0x44
+
+#define STM32_RCC_AHB1_LPENR 0x50
+#define STM32_RCC_AHB2_LPENR 0x54
+#define STM32_RCC_AHB3_LPENR 0x58
+
+#define STM32_RCC_APB1_LPENR 0x60
+#define STM32_RCC_APB2_LPENR 0x64
+
+#define STM32_RCC_BDCR 0x70
+#define STM32_RCC_CSR 0x74
+
+#define STM32_RCC_SSCGR 0x80
+#define STM32_RCC_PLLI2SCFGR 0x84
+#define STM32_RCC_PLLSAI_CFGR 0x88
+#define STM32_RCC_DCKCFGR 0x8C
+#define STM32_RCC_CKGATENR 0x90
+#define STM32_RCC_DCKCFGR2 0x94
+
+#define STM32_RCC_NREGS ((STM32_RCC_DCKCFGR2 >> 2) + 1)
+#define STM32_RCC_PERIPHERAL_SIZE 0x400
+#define STM32_RCC_NIRQS (32 * 5) /* 32 bits per reg, 5 en/rst regs */
+
+#define STM32_RCC_GPIO_IRQ_OFFSET 0
+
+#define TYPE_STM32_RCC "stm32.rcc"
+
+typedef struct STM32RccState STM32RccState;
+
+DECLARE_INSTANCE_CHECKER(STM32RccState, STM32_RCC, TYPE_STM32_RCC)
+
+#define NUM_GPIO_EVENT_IN_LINES 16
+
+struct STM32RccState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+
+ uint32_t regs[STM32_RCC_NREGS];
+
+ qemu_irq enable_irq[STM32_RCC_NIRQS];
+ qemu_irq reset_irq[STM32_RCC_NIRQS];
+};
+
+#endif /* HW_STM32_RCC_H */
Generic RCC class for STM32 devices. It can be used for most of STM32 chips. Note that it only implements enable and reset capabilities. Signed-off-by: Roman Cardenas Rodriguez <rcardenas.rod@gmail.com> --- hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/stm32_rcc.c | 162 ++++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 6 ++ include/hw/misc/stm32_rcc.h | 91 ++++++++++++++++++++ 5 files changed, 263 insertions(+) create mode 100644 hw/misc/stm32_rcc.c create mode 100644 include/hw/misc/stm32_rcc.h