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[v2,1/1] hw/ssi/xilinx_spips: Fix flash erase assert in dual parallel configuration

Message ID 20241001113240.2755645-1-Shivasagar.Myana@amd.com (mailing list archive)
State New, archived
Headers show
Series [v2,1/1] hw/ssi/xilinx_spips: Fix flash erase assert in dual parallel configuration | expand

Commit Message

Shiva sagar Myana Oct. 1, 2024, 11:32 a.m. UTC 
Ensure that the FIFO is checked for emptiness before popping data from it.
Previously, the code directly popped the data from the FIFO without checking, which
could cause an assertion failure:
../util/fifo8.c:67: fifo8_pop: Assertion `fifo->num > 0

Signed-off-by: Shiva sagar Myana <Shivasagar.Myana@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
---
V1->V2: corrected the subject line.

 hw/ssi/xilinx_spips.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
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Patch

diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 71952a410d..adaf404f54 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -620,7 +620,9 @@  static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
         } else if (s->snoop_state == SNOOP_STRIPING ||
                    s->snoop_state == SNOOP_NONE) {
             for (i = 0; i < num_effective_busses(s); ++i) {
-                tx_rx[i] = fifo8_pop(&s->tx_fifo);
+                if (!fifo8_is_empty(&s->tx_fifo)) {
+                    tx_rx[i] = fifo8_pop(&s->tx_fifo);
+                }
             }
             stripe8(tx_rx, num_effective_busses(s), false);
         } else if (s->snoop_state >= SNOOP_ADDR) {