diff mbox series

[v1,1/7] target/riscv: Fix sstatus read and write

Message ID 20241007033400.50163-2-zhiwei_liu@linux.alibaba.com (mailing list archive)
State New, archived
Headers show
Series target/riscv: Support SXL32 on RV64 CPU | expand

Commit Message

LIU Zhiwei Oct. 7, 2024, 3:33 a.m. UTC 
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>

Sstatus is SXLEN bits in length and always has the layout determined by
the SXL configuration, regardless of the current XLEN.

Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Fixes: b550f89457 (target/riscv: Compute mstatus.sd on demand)
Fixes: f310df58bd (target/riscv: Enable uxl field write)
---
 target/riscv/csr.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

Comments

Alistair Francis Oct. 11, 2024, 3:44 a.m. UTC | #1 
On Mon, Oct 7, 2024 at 1:35 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> Sstatus is SXLEN bits in length and always has the layout determined by
> the SXL configuration, regardless of the current XLEN.
>
> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> Fixes: b550f89457 (target/riscv: Compute mstatus.sd on demand)
> Fixes: f310df58bd (target/riscv: Enable uxl field write)

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index ea3560342c..b33cc1ec23 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2893,7 +2893,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
>  {
>      uint64_t mask = sstatus_v1_10_mask;
>      uint64_t sstatus = env->mstatus & mask;
> -    if (env->xl != MXL_RV32 || env->debugger) {
> +    if (riscv_cpu_sxl(env) != MXL_RV32 || env->debugger) {
>          mask |= SSTATUS64_UXL;
>      }
>
> @@ -2905,11 +2905,10 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
>                                     target_ulong *val)
>  {
>      target_ulong mask = (sstatus_v1_10_mask);
> -    if (env->xl != MXL_RV32 || env->debugger) {
> +    if (riscv_cpu_sxl(env) != MXL_RV32 || env->debugger) {
>          mask |= SSTATUS64_UXL;
>      }
> -    /* TODO: Use SXL not MXL. */
> -    *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
> +    *val = add_status_sd(riscv_cpu_sxl(env), env->mstatus & mask);
>      return RISCV_EXCP_NONE;
>  }
>
> @@ -2918,7 +2917,7 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
>  {
>      target_ulong mask = (sstatus_v1_10_mask);
>
> -    if (env->xl != MXL_RV32 || env->debugger) {
> +    if (riscv_cpu_sxl(env) != MXL_RV32 || env->debugger) {
>          if ((val & SSTATUS64_UXL) != 0) {
>              mask |= SSTATUS64_UXL;
>          }
> --
> 2.43.0
>
>
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ea3560342c..b33cc1ec23 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2893,7 +2893,7 @@  static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
 {
     uint64_t mask = sstatus_v1_10_mask;
     uint64_t sstatus = env->mstatus & mask;
-    if (env->xl != MXL_RV32 || env->debugger) {
+    if (riscv_cpu_sxl(env) != MXL_RV32 || env->debugger) {
         mask |= SSTATUS64_UXL;
     }
 
@@ -2905,11 +2905,10 @@  static RISCVException read_sstatus(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
     target_ulong mask = (sstatus_v1_10_mask);
-    if (env->xl != MXL_RV32 || env->debugger) {
+    if (riscv_cpu_sxl(env) != MXL_RV32 || env->debugger) {
         mask |= SSTATUS64_UXL;
     }
-    /* TODO: Use SXL not MXL. */
-    *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
+    *val = add_status_sd(riscv_cpu_sxl(env), env->mstatus & mask);
     return RISCV_EXCP_NONE;
 }
 
@@ -2918,7 +2917,7 @@  static RISCVException write_sstatus(CPURISCVState *env, int csrno,
 {
     target_ulong mask = (sstatus_v1_10_mask);
 
-    if (env->xl != MXL_RV32 || env->debugger) {
+    if (riscv_cpu_sxl(env) != MXL_RV32 || env->debugger) {
         if ((val & SSTATUS64_UXL) != 0) {
             mask |= SSTATUS64_UXL;
         }