Message ID | 20241008225010.1861630-10-debug@rivosinc.com (mailing list archive) |
---|---|
State | New |
Headers | show
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Tue, 08 Oct 2024 15:50:25 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138af962sm60006105ad.26.2024.10.08.15.50.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 15:50:25 -0700 (PDT) From: Deepak Gupta <debug@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, kito.cheng@sifive.com, Deepak Gupta <debug@rivosinc.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PATCH v16 09/20] target/riscv: Expose zicfilp extension as a cpu property Date: Tue, 8 Oct 2024 15:49:59 -0700 Message-ID: <20241008225010.1861630-10-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008225010.1861630-1-debug@rivosinc.com> References: <20241008225010.1861630-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; 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Series |
riscv support for control flow integrity extensions
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expand
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diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 05f727222e..135559fc95 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1469,6 +1469,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), + MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false), MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),