| Message ID | 20241009150855.804605-7-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | accel/tcg: Convert victim tlb to IntervalTree | expand |
On 9/10/24 12:08, Richard Henderson wrote: > Probably never happens, but next patches will assume non-zero length. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > accel/tcg/cputlb.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index fd8da8586f..93b42d18ee 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -801,6 +801,9 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, > * If all bits are significant, and len is small, > * this devolves to tlb_flush_page. > */ > + if (len == 0) { > + return; > + } Maybe clearer to move the check before the comment, otherwise: Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { > tlb_flush_page_by_mmuidx(cpu, addr, idxmap); > return; > @@ -839,6 +842,9 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, > * If all bits are significant, and len is small, > * this devolves to tlb_flush_page. > */ > + if (len == 0) { > + return; > + } > if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { > tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap); > return;
On 10/9/24 08:08, Richard Henderson wrote: > Probably never happens, but next patches will assume non-zero length. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > accel/tcg/cputlb.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index fd8da8586f..93b42d18ee 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -801,6 +801,9 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, > * If all bits are significant, and len is small, > * this devolves to tlb_flush_page. > */ > + if (len == 0) { > + return; > + } > if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { > tlb_flush_page_by_mmuidx(cpu, addr, idxmap); > return; > @@ -839,6 +842,9 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, > * If all bits are significant, and len is small, > * this devolves to tlb_flush_page. > */ > + if (len == 0) { > + return; > + } > if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { > tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap); > return; If this "probably never happens", wouldn't that be better to assert that len is strictly positive?
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index fd8da8586f..93b42d18ee 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -801,6 +801,9 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, * If all bits are significant, and len is small, * this devolves to tlb_flush_page. */ + if (len == 0) { + return; + } if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx(cpu, addr, idxmap); return; @@ -839,6 +842,9 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, * If all bits are significant, and len is small, * this devolves to tlb_flush_page. */ + if (len == 0) { + return; + } if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap); return;
Probably never happens, but next patches will assume non-zero length. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- accel/tcg/cputlb.c | 6 ++++++ 1 file changed, 6 insertions(+)