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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0f6462sm31681145ad.272.2024.10.21.17.11.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Oct 2024 17:11:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, dbarboza@ventanamicro.com, alistair23@gmail.com Subject: [PATCH v7 09/14] tcg/riscv: Accept constant first argument to sub_vec Date: Mon, 21 Oct 2024 17:11:29 -0700 Message-ID: <20241022001134.828724-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241022001134.828724-1-richard.henderson@linaro.org> References: <20241022001134.828724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use vrsub.vi to subtract from a constant. Signed-off-by: Richard Henderson Acked-by: Alistair Francis --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index 97e6ecdb0f..d8ce5414f5 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -25,6 +25,7 @@ C_O0_I2(v, r) C_O1_I1(v, r) C_O1_I1(v, v) C_O1_I2(v, v, v) +C_O1_I2(v, vK, v) C_O1_I2(v, v, vK) C_O1_I2(v, v, vL) C_O1_I4(v, v, vL, vK, vK) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index ce8d6d0293..1ce2f291d3 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -2350,7 +2350,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_sub_vec: set_vtype_len_sew(s, type, vece); - tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2); + if (const_args[1]) { + tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a2, a1); + } else { + tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2); + } break; case INDEX_op_and_vec: set_vtype_len(s, type); @@ -2565,7 +2569,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_xor_vec: return C_O1_I2(v, v, vK); case INDEX_op_sub_vec: - return C_O1_I2(v, v, v); + return C_O1_I2(v, vK, v); case INDEX_op_cmp_vec: return C_O1_I2(v, v, vL); case INDEX_op_cmpsel_vec: