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[82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a912d6545sm652536866b.31.2024.10.24.12.43.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Oct 2024 12:43:14 -0700 (PDT) From: Phil Dennis-Jordan To: qemu-devel@nongnu.org Cc: dirty@apple.com, rbolshakov@ddn.com, Phil Dennis-Jordan Subject: [PATCH 3/4] i386/hvf: Raise exception on error setting APICBASE Date: Thu, 24 Oct 2024 21:43:02 +0200 Message-Id: <20241024194303.32100-4-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20241024194303.32100-1-phil@philjordan.eu> References: <20241024194303.32100-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::133; envelope-from=phil@philjordan.eu; helo=mail-lf1-x133.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When setting the APICBASE MSR to an illegal value, the APIC implementation will return an error. This change forwards that report to the guest as an exception rather than ignoring it when using the hvf accelerator. Signed-off-by: Phil Dennis-Jordan --- target/i386/hvf/x86_emu.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index be675bcfb71..015f760acb3 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -794,9 +794,16 @@ void simulate_wrmsr(CPUX86State *env) switch (msr) { case MSR_IA32_TSC: break; - case MSR_IA32_APICBASE: - cpu_set_apic_base(cpu->apic_state, data); + case MSR_IA32_APICBASE: { + int r; + + r = cpu_set_apic_base(cpu->apic_state, data); + if (r < 0) { + raise_exception(env, EXCP0D_GPF, 0); + } + break; + } case MSR_APIC_START ... MSR_APIC_END: { int ret; int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;