[RFC,12/21] arm/cpu: Store id_mmfr0-5 into the idregs array

Message ID	20241025101959.601048-13-eric.auger@redhat.com (mailing list archive)
State	New
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Eric Auger <eric.auger@redhat.com> To: eric.auger.pro@gmail.com, eric.auger@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: [RFC 12/21] arm/cpu: Store id_mmfr0-5 into the idregs array Date: Fri, 25 Oct 2024 12:17:31 +0200 Message-ID: <20241025101959.601048-13-eric.auger@redhat.com> In-Reply-To: <20241025101959.601048-1-eric.auger@redhat.com> References: <20241025101959.601048-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.263, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	kvm/arm: Introduce a customizable aarch64 KVM host model \| expand [RFC,00/21] kvm/arm: Introduce a customizable aarch64 KVM host model [RFC,01/21] kvm: kvm_get_writable_id_regs [RFC,02/21] arm/cpu: Add sysreg definitions in cpu-sysegs.h [RFC,03/21] arm/cpu: Store aa64isar0 into the idregs arrays [RFC,04/21] arm/cpu: Store aa64isar1/2 into the idregs array [RFC,05/21] arm/cpu: Store aa64drf0/1 into the idregs array [RFC,06/21] arm/cpu: Store aa64mmfr0-3 into the idregs array [RFC,07/21] arm/cpu: Store aa64drf0/1 into the idregs array [RFC,08/21] arm/cpu: Store aa64smfr0 into the idregs array [RFC,09/21] arm/cpu: Store id_isar0-7 into the idregs array [RFC,10/21] arm/cpu: Store id_mfr0/1 into the idregs array [RFC,11/21] arm/cpu: Store id_dfr0/1 into the idregs array [RFC,12/21] arm/cpu: Store id_mmfr0-5 into the idregs array [RFC,13/21] arm/cpu: Add infra to handle generated ID register definitions [RFC,14/21] arm/cpu: Add sysreg generation scripts [RFC,15/21] arm/cpu: Add generated files [RFC,16/21] arm/kvm: Allow reading all the writable ID registers [RFC,17/21] arm/kvm: write back modified ID regs to KVM [RFC,18/21] arm/cpu: Introduce a customizable kvm host cpu model [RFC,19/21] virt: Allow custom vcpu model in arm virt [RFC,20/21] arm-qmp-cmds: introspection for custom model [RFC,21/21] arm/cpu-features: Document custom vcpu model

diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index bd8a24169a..93e5288539 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -282,17 +282,17 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR0, VMSA) >= 4; } static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR3, PAN) != 0; } static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR3, PAN) >= 2; } static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) @@ -318,32 +318,32 @@ static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, HPDS) != 0; } static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, AC2) != 0; } static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, CCIDX) != 0; } static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, XNX) != 0; } static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, EVT) >= 1; } static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2; + return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, EVT) >= 2; } static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8fae42d5b9..30b265e9b0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1071,12 +1071,6 @@ struct ArchCPU { * field by reading the value from the KVM vCPU. */ struct ARMISARegisters { - uint32_t id_mmfr0; - uint32_t id_mmfr1; - uint32_t id_mmfr2; - uint32_t id_mmfr3; - uint32_t id_mmfr4; - uint32_t id_mmfr5; uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 7a11322b2c..3ad4418302 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1284,22 +1284,22 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr0; + return GET_IDREG(idregs, ID_MMFR0); case 0xd54: /* MMFR1. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr1; + return GET_IDREG(idregs, ID_MMFR1); case 0xd58: /* MMFR2. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr2; + return GET_IDREG(idregs, ID_MMFR2); case 0xd5c: /* MMFR3. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr3; + return GET_IDREG(idregs, ID_MMFR3); case 0xd60: /* ISAR0. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6b8fdd8678..57e73fdd38 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -615,10 +615,10 @@ static void aarch64_a57_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x10101105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02102211; + SET_IDREG(idregs, ID_MMFR0, 0x10101105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02102211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); @@ -674,10 +674,10 @@ static void aarch64_a53_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x10101105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02102211; + SET_IDREG(idregs, ID_MMFR0, 0x10101105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02102211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); diff --git a/target/arm/helper.c b/target/arm/helper.c index 81c2caee2c..978b9ed44a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8758,22 +8758,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa32_tid3, - .resetvalue = cpu->isar.id_mmfr0 }, + .resetvalue = GET_IDREG(idregs, ID_MMFR0)}, { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa32_tid3, - .resetvalue = cpu->isar.id_mmfr1 }, + .resetvalue = GET_IDREG(idregs, ID_MMFR1)}, { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa32_tid3, - .resetvalue = cpu->isar.id_mmfr2 }, + .resetvalue = GET_IDREG(idregs, ID_MMFR2)}, { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa32_tid3, - .resetvalue = cpu->isar.id_mmfr3 }, + .resetvalue = GET_IDREG(idregs, ID_MMFR3)}, { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, @@ -8808,7 +8808,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa32_tid3, - .resetvalue = cpu->isar.id_mmfr4 }, + .resetvalue = GET_IDREG(idregs, ID_MMFR4)}, { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, @@ -9092,7 +9092,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = cpu->isar.id_mmfr5 }, + .resetvalue = GET_IDREG(idregs, ID_MMFR5)}, { .name = "RES_0_C0_C3_7", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 144764cc54..bd53554832 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -360,14 +360,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR0_EL1); err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1); err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR0_EL1); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, - ARM64_SYS_REG(3, 0, 0, 1, 4)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, - ARM64_SYS_REG(3, 0, 0, 1, 5)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, - ARM64_SYS_REG(3, 0, 0, 1, 6)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, - ARM64_SYS_REG(3, 0, 0, 1, 7)); + err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR0_EL1); + err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR1_EL1); + err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR2_EL1); + err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR3_EL1); err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR0_EL1); err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR1_EL1); err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR2_EL1); @@ -375,8 +371,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR4_EL1); err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR5_EL1); err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR6_EL1); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, - ARM64_SYS_REG(3, 0, 0, 2, 6)); + err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR4_EL1); err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, ARM64_SYS_REG(3, 0, 0, 3, 0)); @@ -386,8 +381,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 3, 2)); err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_PFR2_EL1); err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR1_EL1); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, - ARM64_SYS_REG(3, 0, 0, 3, 6)); + err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR5_EL1); /* * DBGDIDR is a bit complicated because the kernel doesn't diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 369e3e4c59..cbf1c03d68 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -64,10 +64,10 @@ static void cortex_m0_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00000200); SET_IDREG(idregs, ID_DFR0, 0x00100000); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x00000030; - cpu->isar.id_mmfr1 = 0x00000000; - cpu->isar.id_mmfr2 = 0x00000000; - cpu->isar.id_mmfr3 = 0x00000000; + SET_IDREG(idregs, ID_MMFR0, 0x00000030); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x00000000); + SET_IDREG(idregs, ID_MMFR3, 0x00000000); SET_IDREG(idregs, ID_ISAR0, 0x01141110); SET_IDREG(idregs, ID_ISAR1, 0x02111000); SET_IDREG(idregs, ID_ISAR2, 0x21112231); @@ -90,10 +90,10 @@ static void cortex_m3_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00000200); SET_IDREG(idregs, ID_DFR0, 0x00100000); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x00000030; - cpu->isar.id_mmfr1 = 0x00000000; - cpu->isar.id_mmfr2 = 0x00000000; - cpu->isar.id_mmfr3 = 0x00000000; + SET_IDREG(idregs, ID_MMFR0, 0x00000030); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x00000000); + SET_IDREG(idregs, ID_MMFR3, 0x00000000); SET_IDREG(idregs, ID_ISAR0, 0x01141110); SET_IDREG(idregs, ID_ISAR1, 0x02111000); SET_IDREG(idregs, ID_ISAR2, 0x21112231); @@ -121,10 +121,10 @@ static void cortex_m4_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00000200); SET_IDREG(idregs, ID_DFR0, 0x00100000); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x00000030; - cpu->isar.id_mmfr1 = 0x00000000; - cpu->isar.id_mmfr2 = 0x00000000; - cpu->isar.id_mmfr3 = 0x00000000; + SET_IDREG(idregs, ID_MMFR0, 0x00000030); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x00000000); + SET_IDREG(idregs, ID_MMFR3, 0x00000000); SET_IDREG(idregs, ID_ISAR0, 0x01141110); SET_IDREG(idregs, ID_ISAR1, 0x02111000); SET_IDREG(idregs, ID_ISAR2, 0x21112231); @@ -152,10 +152,10 @@ static void cortex_m7_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00000200); SET_IDREG(idregs, ID_DFR0, 0x00100000); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x00100030; - cpu->isar.id_mmfr1 = 0x00000000; - cpu->isar.id_mmfr2 = 0x01000000; - cpu->isar.id_mmfr3 = 0x00000000; + SET_IDREG(idregs, ID_MMFR0, 0x00100030); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x01000000); + SET_IDREG(idregs, ID_MMFR3, 0x00000000); SET_IDREG(idregs, ID_ISAR0, 0x01101110); SET_IDREG(idregs, ID_ISAR1, 0x02112000); SET_IDREG(idregs, ID_ISAR2, 0x20232231); @@ -185,10 +185,10 @@ static void cortex_m33_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00000210); SET_IDREG(idregs, ID_DFR0, 0x00200000); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x00101F40; - cpu->isar.id_mmfr1 = 0x00000000; - cpu->isar.id_mmfr2 = 0x01000000; - cpu->isar.id_mmfr3 = 0x00000000; + SET_IDREG(idregs, ID_MMFR0, 0x00101F40); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x01000000); + SET_IDREG(idregs, ID_MMFR3, 0x00000000); SET_IDREG(idregs, ID_ISAR0, 0x01101110); SET_IDREG(idregs, ID_ISAR1, 0x02212000); SET_IDREG(idregs, ID_ISAR2, 0x20232232); @@ -223,10 +223,10 @@ static void cortex_m55_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00000230); SET_IDREG(idregs, ID_DFR0, 0x10200000); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x00111040; - cpu->isar.id_mmfr1 = 0x00000000; - cpu->isar.id_mmfr2 = 0x01000000; - cpu->isar.id_mmfr3 = 0x00000011; + SET_IDREG(idregs, ID_MMFR0, 0x00111040); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x01000000); + SET_IDREG(idregs, ID_MMFR3, 0x00000011); SET_IDREG(idregs, ID_ISAR0, 0x01103110); SET_IDREG(idregs, ID_ISAR1, 0x02212000); SET_IDREG(idregs, ID_ISAR2, 0x20232232); diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index d1712216ff..6620260480 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -55,21 +55,17 @@ void aa32_max_features(ARMCPU *cpu) t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 = t; - t = cpu->isar.id_mmfr3; - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ - cpu->isar.id_mmfr3 = t; + FIELD_DP32_IDREG(idregs, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ - t = cpu->isar.id_mmfr4; + t = GET_IDREG(idregs, ID_MMFR4); t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ - cpu->isar.id_mmfr4 = t; + SET_IDREG(idregs, ID_MMFR4, t); - t = cpu->isar.id_mmfr5; - t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ - cpu->isar.id_mmfr5 = t; + FIELD_DP32_IDREG(idregs, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ t = GET_IDREG(idregs, ID_PFR0); t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ @@ -230,9 +226,9 @@ static void arm1136_r2_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x1); SET_IDREG(idregs, ID_DFR0, 0x2); cpu->id_afr0 = 0x3; - cpu->isar.id_mmfr0 = 0x01130003; - cpu->isar.id_mmfr1 = 0x10030302; - cpu->isar.id_mmfr2 = 0x01222110; + SET_IDREG(idregs, ID_MMFR0, 0x01130003); + SET_IDREG(idregs, ID_MMFR1, 0x10030302); + SET_IDREG(idregs, ID_MMFR2, 0x01222110); SET_IDREG(idregs, ID_ISAR0, 0x00140011); SET_IDREG(idregs, ID_ISAR1, 0x12002111); SET_IDREG(idregs, ID_ISAR2, 0x11231111); @@ -262,9 +258,9 @@ static void arm1136_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x1); SET_IDREG(idregs, ID_DFR0, 0x2); cpu->id_afr0 = 0x3; - cpu->isar.id_mmfr0 = 0x01130003; - cpu->isar.id_mmfr1 = 0x10030302; - cpu->isar.id_mmfr2 = 0x01222110; + SET_IDREG(idregs, ID_MMFR0, 0x01130003); + SET_IDREG(idregs, ID_MMFR1, 0x10030302); + SET_IDREG(idregs, ID_MMFR2, 0x01222110); SET_IDREG(idregs, ID_ISAR0, 0x00140011); SET_IDREG(idregs, ID_ISAR1, 0x12002111); SET_IDREG(idregs, ID_ISAR2, 0x11231111); @@ -295,9 +291,9 @@ static void arm1176_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x11); SET_IDREG(idregs, ID_DFR0, 0x33); cpu->id_afr0 = 0; - cpu->isar.id_mmfr0 = 0x01130003; - cpu->isar.id_mmfr1 = 0x10030302; - cpu->isar.id_mmfr2 = 0x01222100; + SET_IDREG(idregs, ID_MMFR0, 0x01130003); + SET_IDREG(idregs, ID_MMFR1, 0x10030302); + SET_IDREG(idregs, ID_MMFR2, 0x01222100); SET_IDREG(idregs, ID_ISAR0, 0x0140011); SET_IDREG(idregs, ID_ISAR1, 0x12002111); SET_IDREG(idregs, ID_ISAR2, 0x11231121); @@ -325,9 +321,9 @@ static void arm11mpcore_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x1); SET_IDREG(idregs, ID_DFR0, 0); cpu->id_afr0 = 0x2; - cpu->isar.id_mmfr0 = 0x01100103; - cpu->isar.id_mmfr1 = 0x10020302; - cpu->isar.id_mmfr2 = 0x01222000; + SET_IDREG(idregs, ID_MMFR0, 0x01100103); + SET_IDREG(idregs, ID_MMFR1, 0x10020302); + SET_IDREG(idregs, ID_MMFR2, 0x01222000); SET_IDREG(idregs, ID_ISAR0, 0x00100011); SET_IDREG(idregs, ID_ISAR1, 0x12002111); SET_IDREG(idregs, ID_ISAR2, 0x11221011); @@ -365,10 +361,10 @@ static void cortex_a8_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x11); SET_IDREG(idregs, ID_DFR0, 0x400); cpu->id_afr0 = 0; - cpu->isar.id_mmfr0 = 0x31100003; - cpu->isar.id_mmfr1 = 0x20000000; - cpu->isar.id_mmfr2 = 0x01202000; - cpu->isar.id_mmfr3 = 0x11; + SET_IDREG(idregs, ID_MMFR0, 0x31100003); + SET_IDREG(idregs, ID_MMFR1, 0x20000000); + SET_IDREG(idregs, ID_MMFR2, 0x01202000); + SET_IDREG(idregs, ID_MMFR3, 0x11); SET_IDREG(idregs, ID_ISAR0, 0x00101111); SET_IDREG(idregs, ID_ISAR1, 0x12112111); SET_IDREG(idregs, ID_ISAR2, 0x21232031); @@ -441,10 +437,10 @@ static void cortex_a9_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x11); SET_IDREG(idregs, ID_DFR0, 0x000); cpu->id_afr0 = 0; - cpu->isar.id_mmfr0 = 0x00100103; - cpu->isar.id_mmfr1 = 0x20000000; - cpu->isar.id_mmfr2 = 0x01230000; - cpu->isar.id_mmfr3 = 0x00002111; + SET_IDREG(idregs, ID_MMFR0, 0x00100103); + SET_IDREG(idregs, ID_MMFR1, 0x20000000); + SET_IDREG(idregs, ID_MMFR2, 0x01230000); + SET_IDREG(idregs, ID_MMFR3, 0x00002111); SET_IDREG(idregs, ID_ISAR0, 0x00101111); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232041); @@ -507,10 +503,10 @@ static void cortex_a7_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x02010555); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x10101105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01240000; - cpu->isar.id_mmfr3 = 0x02102211; + SET_IDREG(idregs, ID_MMFR0, 0x10101105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01240000); + SET_IDREG(idregs, ID_MMFR3, 0x02102211); /* * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. @@ -559,10 +555,10 @@ static void cortex_a15_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x02010555); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x10201105; - cpu->isar.id_mmfr1 = 0x20000000; - cpu->isar.id_mmfr2 = 0x01240000; - cpu->isar.id_mmfr3 = 0x02102211; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x20000000); + SET_IDREG(idregs, ID_MMFR2, 0x01240000); + SET_IDREG(idregs, ID_MMFR3, 0x02102211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232041); @@ -603,10 +599,10 @@ static void cortex_r5_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x001); SET_IDREG(idregs, ID_DFR0, 0x010400); cpu->id_afr0 = 0x0; - cpu->isar.id_mmfr0 = 0x0210030; - cpu->isar.id_mmfr1 = 0x00000000; - cpu->isar.id_mmfr2 = 0x01200000; - cpu->isar.id_mmfr3 = 0x0211; + SET_IDREG(idregs, ID_MMFR0, 0x0210030); + SET_IDREG(idregs, ID_MMFR1, 0x00000000); + SET_IDREG(idregs, ID_MMFR2, 0x01200000); + SET_IDREG(idregs, ID_MMFR3, 0x0211); SET_IDREG(idregs, ID_ISAR0, 0x02101111); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232141); @@ -750,11 +746,11 @@ static void cortex_r52_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x10111001); SET_IDREG(idregs, ID_DFR0, 0x03010006); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x00211040; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01200000; - cpu->isar.id_mmfr3 = 0xf0102211; - cpu->isar.id_mmfr4 = 0x00000010; + SET_IDREG(idregs, ID_MMFR0, 0x00211040); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01200000); + SET_IDREG(idregs, ID_MMFR3, 0xf0102211); + SET_IDREG(idregs, ID_MMFR4, 0x00000010); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232142); @@ -982,10 +978,10 @@ static void arm_max_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x10101105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02102211; + ET_IDREG(idregs, ID_MMFR0, 0x10101105); + ET_IDREG(idregs, ID_MMFR1, 0x40000000); + ET_IDREG(idregs, ID_MMFR2, 0x01260000); + ET_IDREG(idregs, ID_MMFR3, 0x02102211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index aee36fabc1..ac54fd2083 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -79,10 +79,10 @@ static void aarch64_a35_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 = 0; - cpu->isar.id_mmfr0 = 0x10201105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02102211; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02102211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); @@ -259,11 +259,11 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(idregs, ID_ISAR4, 0x00011142); SET_IDREG(idregs, ID_ISAR5, 0x01011121); SET_IDREG(idregs, ID_ISAR6, 0x00000010); - cpu->isar.id_mmfr0 = 0x10201105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02122211; - cpu->isar.id_mmfr4 = 0x00021110; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02122211); + SET_IDREG(idregs, ID_MMFR4, 0x00021110); SET_IDREG(idregs, ID_PFR0, 0x10010131); SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_PFR2, 0x00000011); @@ -319,10 +319,10 @@ static void aarch64_a72_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00011011); SET_IDREG(idregs, ID_DFR0, 0x03010066); cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x10201105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02102211; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02102211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); @@ -386,11 +386,11 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(idregs, ID_ISAR4, 0x00010142); SET_IDREG(idregs, ID_ISAR5, 0x01011121); SET_IDREG(idregs, ID_ISAR6, 0x00000010); - cpu->isar.id_mmfr0 = 0x10201105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02122211; - cpu->isar.id_mmfr4 = 0x00021110; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02122211); + SET_IDREG(idregs, ID_MMFR4, 0x00021110); SET_IDREG(idregs, ID_PFR0, 0x10010131); SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(idregs, ID_PFR2, 0x00000011); @@ -628,11 +628,11 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(idregs, ID_ISAR4, 0x00010142); SET_IDREG(idregs, ID_ISAR5, 0x01011121); SET_IDREG(idregs, ID_ISAR6, 0x00000010); - cpu->isar.id_mmfr0 = 0x10201105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02122211; - cpu->isar.id_mmfr4 = 0x00021110; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02122211); + SET_IDREG(idregs, ID_MMFR4, 0x00021110); SET_IDREG(idregs, ID_PFR0, 0x10010131); SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(idregs, ID_PFR2, 0x00000011); @@ -704,11 +704,11 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(idregs, ID_ISAR4, 0x00010142); SET_IDREG(idregs, ID_ISAR5, 0x11011121); SET_IDREG(idregs, ID_ISAR6, 0x01100111); - cpu->isar.id_mmfr0 = 0x10201105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02122211; - cpu->isar.id_mmfr4 = 0x01021110; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02122211); + SET_IDREG(idregs, ID_MMFR4, 0x01021110); SET_IDREG(idregs, ID_PFR0, 0x21110131); SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(idregs, ID_PFR2, 0x00000011); @@ -911,17 +911,17 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(idregs, ID_DFR0, 0x16011099); cpu->id_afr0 = 0; - cpu->isar.id_mmfr0 = 0x10201105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02122211; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02122211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); SET_IDREG(idregs, ID_ISAR3, 0x01112131); SET_IDREG(idregs, ID_ISAR4, 0x00010142); SET_IDREG(idregs, ID_ISAR5, 0x11011121); /* with Crypto */ - cpu->isar.id_mmfr4 = 0x21021110; + SET_IDREG(idregs, ID_MMFR4, 0x21021110); SET_IDREG(idregs, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 = 0x10110222; cpu->isar.mvfr1 = 0x13211111; @@ -1011,17 +1011,17 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(idregs, ID_DFR0, 0x16011099); cpu->id_afr0 = 0; - cpu->isar.id_mmfr0 = 0x10201105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01260000; - cpu->isar.id_mmfr3 = 0x02122211; + SET_IDREG(idregs, ID_MMFR0, 0x10201105); + SET_IDREG(idregs, ID_MMFR1, 0x40000000); + SET_IDREG(idregs, ID_MMFR2, 0x01260000); + SET_IDREG(idregs, ID_MMFR3, 0x02122211); SET_IDREG(idregs, ID_ISAR0, 0x02101110); SET_IDREG(idregs, ID_ISAR1, 0x13112111); SET_IDREG(idregs, ID_ISAR2, 0x21232042); SET_IDREG(idregs, ID_ISAR3, 0x01112131); SET_IDREG(idregs, ID_ISAR4, 0x00010142); SET_IDREG(idregs, ID_ISAR5, 0x11011121); /* with Crypto */ - cpu->isar.id_mmfr4 = 0x01021110; + SET_IDREG(idregs, ID_MMFR4, 0x01021110); SET_IDREG(idregs, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 = 0x10110222; cpu->isar.mvfr1 = 0x13211111;

[RFC,12/21] arm/cpu: Store id_mmfr0-5 into the idregs array

Commit Message

Patch