| Message ID | 20241029091729.3317512-4-jamin_lin@aspeedtech.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Support RTC for AST2700 | expand |
On Tue, 2024-10-29 at 17:17 +0800, Jamin Lin wrote: > According to the datasheet of AST2600 description, interrupt status > set by HW > and clear to "0" by software writing "1" on the specific bit. > > Therefore, if firmware set the specific bit "1" in the interrupt > status > register(0x34), the specific bit of "s->irq_sts" should be cleared 0. > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Hah, the datasheet table for the register uses `RW` to describe the bits and not `W1C`, but there's a foot-note in the table that says they're W1C bits. Fixes: fadefada4d07 ("aspeed/timer: Add support for IRQ status register on the AST2600") Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Thanks, Andrew
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 5af268ea9e..149f7cc5a6 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -580,7 +580,7 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset, switch (offset) { case 0x34: - s->irq_sts &= tv; + s->irq_sts &= ~tv; break; case 0x3C: aspeed_timer_set_ctrl(s, s->ctrl & ~tv);
According to the datasheet of AST2600 description, interrupt status set by HW and clear to "0" by software writing "1" on the specific bit. Therefore, if firmware set the specific bit "1" in the interrupt status register(0x34), the specific bit of "s->irq_sts" should be cleared 0. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- hw/timer/aspeed_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)