diff mbox series

[PULL,12/50] target/riscv: Set vtype.vill on CPU reset

Message ID	20241031035319.731906-13-alistair.francis@wdc.com (mailing list archive)
State	New
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Rob Bradford <rbradford@rivosinc.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 12/50] target/riscv: Set vtype.vill on CPU reset Date: Thu, 31 Oct 2024 13:52:40 +1000 Message-ID: <20241031035319.731906-13-alistair.francis@wdc.com> In-Reply-To: <20241031035319.731906-1-alistair.francis@wdc.com> References: <20241031035319.731906-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT \| expand [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT [PULL,02/50] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI [PULL,03/50] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 [PULL,04/50] target/riscv: Correct SXL return value for RV32 in RV64 QEMU [PULL,05/50] target/riscv: Detect sxl to set bit width for RV32 in RV64 [PULL,06/50] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU [PULL,07/50] target/riscv: Enable RV32 CPU support in RV64 QEMU [PULL,08/50] target/riscv: Add max32 CPU for RV64 QEMU [PULL,09/50] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU [PULL,10/50] hw/intc: Make zeroth priority register read-only [PULL,11/50] hw/intc: Don't clear pending bits on IRQ lowering [PULL,12/50] target/riscv: Set vtype.vill on CPU reset [PULL,13/50] hw/intc/riscv_aplic: Check and update pending when write sourcecfg [PULL,14/50] hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all [PULL,15/50] hw/char: sifive_uart: Print uart characters async [PULL,16/50] target/riscv: expose *envcfg csr and priv to qemu-user as well [PULL,17/50] target/riscv: Add zicfilp extension [PULL,18/50] target/riscv: Introduce elp state and enabling controls for zicfilp [PULL,19/50] target/riscv: save and restore elp state on priv transitions [PULL,20/50] target/riscv: additional code information for sw check [PULL,21/50] target/riscv: tracking indirect branches (fcfi) for zicfilp [PULL,22/50] target/riscv: zicfilp `lpad` impl and branch tracking [PULL,23/50] disas/riscv: enable `lpad` disassembly [PULL,24/50] target/riscv: Expose zicfilp extension as a cpu property [PULL,25/50] target/riscv: Add zicfiss extension [PULL,26/50] target/riscv: introduce ssp and enabling controls for zicfiss [PULL,27/50] target/riscv: tb flag for shadow stack instructions [PULL,28/50] target/riscv: mmu changes for zicfiss shadow stack protection [PULL,29/50] target/riscv: AMO operations always raise store/AMO fault [PULL,30/50] target/riscv: update `decode_save_opc` to store extra word2 [PULL,31/50] target/riscv: implement zicfiss instructions [PULL,32/50] target/riscv: compressed encodings for sspush and sspopchk [PULL,33/50] disas/riscv: enable disassembly for zicfiss instructions [PULL,34/50] disas/riscv: enable disassembly for compressed sspush/sspopchk [PULL,35/50] target/riscv: Expose zicfiss extension as a cpu property [PULL,36/50] exec/memtxattr: add process identifier to the transaction attributes [PULL,37/50] hw/riscv: add riscv-iommu-bits.h [PULL,38/50] hw/riscv: add RISC-V IOMMU base emulation [PULL,39/50] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device [PULL,40/50] hw/riscv: add riscv-iommu-pci reference device [PULL,41/50] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug [PULL,42/50] test/qtest: add riscv-iommu-pci tests [PULL,43/50] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) [PULL,44/50] hw/riscv/riscv-iommu: add ATS support [PULL,45/50] hw/riscv/riscv-iommu: add DBG support [PULL,46/50] qtest/riscv-iommu-test: add init queues test [PULL,47/50] docs/specs: add riscv-iommu [PULL,48/50] target/riscv/kvm: set 'aia_mode' to default in error path [PULL,49/50] target/riscv/kvm: clarify how 'riscv-aia' default works [PULL,50/50] target/riscv: Fix vcompress with rvv_ta_all_1s

Commit Message

Alistair Francis Oct. 31, 2024, 3:52 a.m. UTC

From: Rob Bradford <rbradford@rivosinc.com>

The RISC-V unprivileged specification "31.3.11. State of Vector
Extension at Reset" has a note that recommends vtype.vill be set on
reset as part of ensuring that the vector extension have a consistent
state at reset.

This change now makes QEMU consistent with Spike which sets vtype.vill
on reset.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240930165258.72258-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0c8e017f71..2a78cd639b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1010,6 +1010,7 @@  static void riscv_cpu_reset_hold(Object *obj, ResetType type)
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
+    env->vill = true;
 
 #ifndef CONFIG_USER_ONLY
     if (cpu->cfg.debug) {