Message ID | 20241031035319.731906-36-alistair.francis@wdc.com (mailing list archive) |
---|---|
State | New |
Headers | show
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Series |
[PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT
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diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index afdba29995..f219f0c3b5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1475,6 +1475,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false), + MULTI_EXT_CFG_BOOL("zicfiss", ext_zicfiss, false), MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),