From patchwork Thu Oct 31 17:51:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13858281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7DBED767F2 for ; Thu, 31 Oct 2024 18:02:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t6ZM6-0000is-LD; Thu, 31 Oct 2024 13:53:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6ZM2-0000TN-LL for qemu-devel@nongnu.org; Thu, 31 Oct 2024 13:53:07 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6ZM0-0007Mb-Sd for qemu-devel@nongnu.org; Thu, 31 Oct 2024 13:53:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1730397184; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OytefNi0XjPduWjiCssRXrev09eWdMweqq0y4XRkrq0=; b=dW87q8ThdnmK7UJp63ZCUsLxsqSZjWyTZ1xEOfDvbjmCyaXkf3DS/UdOWxQhyIW6BEXe1Q C+uBoN7OL8H39AxitXOkwqzaSx/PHIhDdSH/S9hx/anO1F7DeFAg6/Ha9AdK5syprk1TYu quYbNnpGuzgr+4+Wb9xHSmmvTuoaIDI= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-20-xbcoYmKmMzWZdFxVnpuf8A-1; Thu, 31 Oct 2024 13:53:02 -0400 X-MC-Unique: xbcoYmKmMzWZdFxVnpuf8A-1 Received: by mail-wr1-f72.google.com with SMTP id ffacd0b85a97d-37d3e8dccc9so629648f8f.1 for ; Thu, 31 Oct 2024 10:53:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730397180; x=1731001980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OytefNi0XjPduWjiCssRXrev09eWdMweqq0y4XRkrq0=; b=faieu7TQA+25TDIgfxhyf8p0vTc8YOPE6nmQfxEbXoppMlnpQ6IRcbNebNwzwkj6mX Mzw+4labYkfF37FVc1iAwPBF749YHqp0hfK6dYFPg0xTG1X81XzXHEr2CoOXAAdxPpub rgiC76VV0qBmc8jcuhbg8YFW0tyFCjFN3UD6baGuD4IJ3YWsAk0Rvggy/w6nZKSEV1h3 Yn8qX05ftGUOGZx128V0FaNXyn6hGxe5jAnXQpYFJXXgTd0WWwQzZSFoopmqy2kDev2g eKkAmAQSvSpZKMzF0WQA6C0IyeWg10A+hYTrjVmnxRucu5uZSbr74Moou1DeOMIviPqT D5aQ== X-Gm-Message-State: AOJu0Yx/r9b1GQUmsH59JlMIfYxxfAQgLx4c/gZiLH+q42HQlosb0WsO FQB7ducS2IeEuD3yYwTHZtfMuPVVAz7pv80h3XJ6RMsVKK56H+gQCrlcA8VdpTMboj0OmK1tbBo HcA5Obz+sl+aYfPlJyUajHWWeq4vmSCCxs9jts7e+X84gJ+0G8ACBl7Qp1SKa1cONV+OFC81cdL nik2rm4aRBZZsAaz7x9qsNAqV44UbAcdvceTXMgug= X-Received: by 2002:a5d:64c8:0:b0:37c:cc96:d1ce with SMTP id ffacd0b85a97d-381be7c863amr3611600f8f.24.1730397180261; Thu, 31 Oct 2024 10:53:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEGthLsuZ3dNzuuob55FcOzm1op8cu4vGdTL/ErWgv5yNa8LqnTqdfT/ghJNi/x70/wbIRi8w== X-Received: by 2002:a5d:64c8:0:b0:37c:cc96:d1ce with SMTP id ffacd0b85a97d-381be7c863amr3611581f8f.24.1730397179767; Thu, 31 Oct 2024 10:52:59 -0700 (PDT) Received: from [192.168.10.3] ([151.49.226.83]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd8e7f33sm63968315e9.6.2024.10.31.10.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Oct 2024 10:52:59 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Phil Dennis-Jordan Subject: [PULL 20/49] target/i386/hvf: fix handling of XSAVE-related CPUID bits Date: Thu, 31 Oct 2024 18:51:44 +0100 Message-ID: <20241031175214.214455-21-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241031175214.214455-1-pbonzini@redhat.com> References: <20241031175214.214455-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.366, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The call to xgetbv() is passing the ecx value for cpuid function 0xD, index 0. The xgetbv call thus returns false (OSXSAVE is bit 27, which is well out of the range of CPUID[0xD,0].ECX) and eax is not modified. While fixing it, cache the whole computation of supported XCR0 bits since it will be used for more than just CPUID leaf 0xD. Furthermore, unsupported subleafs of CPUID 0xD (including all those corresponding to zero bits in host's XCR0) must be hidden; if OSXSAVE is not set at all, the whole of CPUID leaf 0xD plus the XSAVE bit must be hidden. Finally, unconditionally drop XSTATE_BNDREGS_MASK and XSTATE_BNDCSR_MASK; real hardware will only show them if the MPX bit is set in CPUID; this is never the case for hvf_get_supported_cpuid() because QEMU's Hypervisor.framework support does not handle the VMX fields related to MPX (even in the unlikely possibility that the host has MPX enabled). So hide those bits in the new cache_host_xcr0(). Cc: Phil Dennis-Jordan Signed-off-by: Paolo Bonzini --- host/include/i386/host/cpuinfo.h | 1 + target/i386/hvf/x86_cpuid.c | 56 +++++++++++++++++++------------- util/cpuinfo-i386.c | 1 + 3 files changed, 35 insertions(+), 23 deletions(-) diff --git a/host/include/i386/host/cpuinfo.h b/host/include/i386/host/cpuinfo.h index 81771733eaa..9541a64da61 100644 --- a/host/include/i386/host/cpuinfo.h +++ b/host/include/i386/host/cpuinfo.h @@ -9,6 +9,7 @@ /* Digested version of */ #define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ +#define CPUINFO_OSXSAVE (1u << 1) #define CPUINFO_MOVBE (1u << 2) #define CPUINFO_LZCNT (1u << 3) #define CPUINFO_POPCNT (1u << 4) diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c index e56cd8411ba..3a116548a3d 100644 --- a/target/i386/hvf/x86_cpuid.c +++ b/target/i386/hvf/x86_cpuid.c @@ -21,28 +21,38 @@ */ #include "qemu/osdep.h" +#include "qemu/cpuid.h" +#include "host/cpuinfo.h" #include "cpu.h" #include "x86.h" #include "vmx.h" #include "sysemu/hvf.h" #include "hvf-i386.h" -static bool xgetbv(uint32_t cpuid_ecx, uint32_t idx, uint64_t *xcr) +static bool cached_xcr0; +static uint64_t supported_xcr0; + +static void cache_host_xcr0() { - uint32_t xcrl, xcrh; - - if (cpuid_ecx & CPUID_EXT_OSXSAVE) { - /* - * The xgetbv instruction is not available to older versions of - * the assembler, so we encode the instruction manually. - */ - asm(".byte 0x0f, 0x01, 0xd0" : "=a" (xcrl), "=d" (xcrh) : "c" (idx)); - - *xcr = (((uint64_t)xcrh) << 32) | xcrl; - return true; + if (cached_xcr0) { + return; } - return false; + if (cpuinfo & CPUINFO_OSXSAVE) { + uint64_t host_xcr0 = xgetbv_low(0); + + /* Only show xcr0 bits corresponding to usable features. */ + supported_xcr0 = host_xcr0 & (XSTATE_FP_MASK | + XSTATE_SSE_MASK | XSTATE_YMM_MASK | + XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | + XSTATE_Hi16_ZMM_MASK); + if ((supported_xcr0 & (XSTATE_FP_MASK | XSTATE_SSE_MASK)) != + (XSTATE_FP_MASK | XSTATE_SSE_MASK)) { + supported_xcr0 = 0; + } + } + + cached_xcr0 = true; } uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, @@ -51,6 +61,7 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, uint64_t cap; uint32_t eax, ebx, ecx, edx; + cache_host_xcr0(); host_cpuid(func, idx, &eax, &ebx, &ecx, &edx); switch (func) { @@ -66,7 +77,8 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, ecx &= CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE | - CPUID_EXT_POPCNT | CPUID_EXT_AES | CPUID_EXT_XSAVE | + CPUID_EXT_POPCNT | CPUID_EXT_AES | + (supported_xcr0 ? CPUID_EXT_XSAVE : 0) | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND; ecx |= CPUID_EXT_HYPERVISOR; break; @@ -107,16 +119,14 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, eax = 0; break; case 0xD: + if (!supported_xcr0 || + (idx > 1 && !(supported_xcr0 & (1 << idx)))) { + eax = ebx = ecx = edx = 0; + break; + } + if (idx == 0) { - uint64_t host_xcr0; - if (xgetbv(ecx, 0, &host_xcr0)) { - uint64_t supp_xcr0 = host_xcr0 & (XSTATE_FP_MASK | - XSTATE_SSE_MASK | XSTATE_YMM_MASK | - XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | - XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | - XSTATE_Hi16_ZMM_MASK); - eax &= supp_xcr0; - } + eax = supported_xcr0; } else if (idx == 1) { hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap); eax &= CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1; diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c index 90f92a42dc8..c8c8a1b3705 100644 --- a/util/cpuinfo-i386.c +++ b/util/cpuinfo-i386.c @@ -35,6 +35,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) __cpuid(1, a, b, c, d); info |= (d & bit_SSE2 ? CPUINFO_SSE2 : 0); + info |= (c & bit_OSXSAVE ? CPUINFO_OSXSAVE : 0); info |= (c & bit_MOVBE ? CPUINFO_MOVBE : 0); info |= (c & bit_POPCNT ? CPUINFO_POPCNT : 0); info |= (c & bit_PCLMUL ? CPUINFO_PCLMUL : 0);