@@ -48,6 +48,8 @@
#define NPCM750_EVB_POWER_ON_STRAPS ( \
NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN)
#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
+#define QUANTA_GSZ_POWER_ON_STRAPS ( \
+ NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB)
#define QUANTA_GBS_POWER_ON_STRAPS ( \
NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB)
#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
@@ -269,6 +271,129 @@ static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
}
+static void quanta_gsz_i2c_init(NPCM7xxState *soc)
+{
+ DeviceState *dev;
+ I2CSlave *i2c_mux;
+
+ /* i2c1 */
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), TYPE_PCA9548,
+ 0x75);
+ /* pca6416@0x20 */
+ dev = DEVICE(i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 3),
+ "pca6416", 0x20));
+ object_property_set_uint(OBJECT(dev), "gpio_config", 0xF00, &error_abort);
+ object_property_set_uint(OBJECT(dev), "gpio_input", 0xF00, &error_abort);
+
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1),
+ TYPE_PCA9548, 0x77);
+
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), "raa229004", 0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), "raa229004", 0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "isl69260", 0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 3), "isl69260", 0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "isl69260", 0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "isl69260", 0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), "adm1272", 0x1f);
+
+ /* i2c2 */
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2),
+ TYPE_PCA9548, 0x77);
+ /* - channel 0: tps546d24 @25
+ * - channel 1: delta,dps800 @69
+ */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), "raa228000", 0x68);
+ /* - channel 2: delta,dps800 @68 */
+ /* max31725 is compatible with tmp105. */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x5c);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x5c);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), "tmp105", 0x5c);
+
+ /* i2c3 */
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), TYPE_PCA9548,
+ 0x77);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "pca9538", 0x72);
+
+ /* i2c4 */
+ /* mobo_fru_1 */
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 4), 0x50, 8192);
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4),
+ TYPE_PCA9548, 0x77);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), "max34451", 0x59);
+ /* mobo_fru_2 */
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 2), 0x55, 32768);
+
+ dev = DEVICE(i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 3),
+ "pca6416", 0x20));
+ object_property_set_uint(OBJECT(dev), "gpio_config", 0x4000, &error_abort);
+ object_property_set_uint(OBJECT(dev), "gpio_input", 0x4000, &error_abort);
+
+ dev = DEVICE(i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4),
+ "pca6416", 0x20));
+ object_property_set_uint(OBJECT(dev), "gpio_config", 0xFFFF, &error_abort);
+ object_property_set_uint(OBJECT(dev), "gpio_input", 0x0000, &error_abort);
+
+ /* pdb_fru */
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 6), 0x55, 8192);
+
+ /* i2c5 */
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 5), TYPE_PCA9548,
+ 0x77);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "pca9538", 0x72);
+
+ /* i2c6 */
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), TYPE_PCA9548,
+ 0x77);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "pca9538", 0x72);
+
+ /* i2c7 */
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 7), TYPE_PCA9548,
+ 0x77);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "pca9538", 0x72);
+
+ /* i2c8 */
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 8), TYPE_PCA9548,
+ 0x77);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "pca9538", 0x72);
+
+ /* i2c9 */
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 9), TYPE_PCA9548,
+ 0x77);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "pca9538", 0x72);
+
+ /* i2c10 */
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 10),
+ TYPE_PCA9548, 0x77);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), "pca9538", 0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "pca9538", 0x72);
+ /* i2c11 */
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 11),
+ TYPE_PCA9548, 0x77);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "pca9538", 0x72);
+
+ /* i2c12 */
+
+ /* i2c13 */
+ i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13), "pca6416", 0x22);
+
+ /* i2c14 */
+ /* LEDs and PE Resets */
+ i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 14), "pca6416", 0x20);
+
+ /* bmc_fru_1 */
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 14), 0x55, 8192);
+
+ i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 14),
+ TYPE_PCA9548, 0x77);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), "max34451", 0x59);
+
+ /* max31725 is compatible with tmp105 */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x5c);
+
+ /* i2c15 */
+ i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 15), TYPE_PCA9546, 0x75);
+}
+
static void quanta_gbs_i2c_init(NPCM7xxState *soc)
{
/*
@@ -392,6 +517,25 @@ static void quanta_gsj_init(MachineState *machine)
npcm7xx_load_kernel(machine, soc);
}
+static void quanta_gsz_init(MachineState *machine)
+{
+ NPCM7xxState *soc;
+
+ soc = npcm7xx_create_soc(machine, QUANTA_GSZ_POWER_ON_STRAPS);
+ npcm7xx_connect_dram(soc, machine->ram);
+ qdev_realize(DEVICE(soc), NULL, &error_fatal);
+
+ npcm7xx_load_bootrom(machine, soc);
+ npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f",
+ drive_get(IF_MTD, 0, 0));
+ npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f",
+ drive_get(IF_MTD, 3, 0));
+
+ quanta_gsz_i2c_init(soc);
+ sdhci_attach_drive(&soc->mmc.sdhci, 0);
+ npcm7xx_load_kernel(machine, soc);
+}
+
static void quanta_gbs_init(MachineState *machine)
{
NPCM7xxState *soc;
@@ -496,6 +640,18 @@ static void gsj_machine_class_init(ObjectClass *oc, void *data)
mc->default_ram_size = 512 * MiB;
};
+static void gsz_machine_class_init(ObjectClass *oc, void *data)
+{
+ NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
+
+ mc->desc = "Quanta GSZ (Cortex-A9)";
+ mc->init = quanta_gsz_init;
+ mc->default_ram_size = 1 * GiB;
+}
+
static void gbs_bmc_machine_class_init(ObjectClass *oc, void *data)
{
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
@@ -548,6 +704,10 @@ static const TypeInfo npcm7xx_machine_types[] = {
.name = MACHINE_TYPE_NAME("quanta-gsj"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = gsj_machine_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("quanta-gsz-bmc"),
+ .parent = TYPE_NPCM7XX_MACHINE,
+ .class_init = gsz_machine_class_init,
}, {
.name = MACHINE_TYPE_NAME("quanta-gbs-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
This patch adds the quanta-gsz-bmc target, a current Google machine of the day. This machine will be used as a platform to enable features such as the PECI bmc interface, and Intel eSPI virtual wire interface in QEMU. Signed-off-by: Titus Rwantare <titusr@google.com> --- hw/arm/npcm7xx_boards.c | 160 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+)