[Stable-7.2.15,24/33] target/riscv: Correct SXL return value for RV32 in RV64 QEMU

Commit Message

Michael Tokarev Nov. 9, 2024, 6:38 a.m. UTC

From: TANG Tiancheng <[e-mail]>

Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.

Signed-off-by: TANG Tiancheng <[e-mail]>
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
Message-ID: <[e-mail]>
Signed-off-by: Alistair Francis <[e-mail]>
(cherry picked from commit 929e4277c128772bad41cc795995f754cb9991af)
Signed-off-by: Michael Tokarev <[e-mail]>

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3a9e25053f..039f25dc6e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -675,8 +675,11 @@  static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
 #ifdef CONFIG_USER_ONLY
     return env->misa_mxl;
 #else
-    return get_field(env->mstatus, MSTATUS64_SXL);
+    if (env->misa_mxl != MXL_RV32) {
+        return get_field(env->mstatus, MSTATUS64_SXL);
+    }
 #endif
+    return MXL_RV32;
 }
 #endif