[Stable-9.0.4,43/57] target/riscv: Set vtype.vill on CPU reset

Commit Message

Michael Tokarev Nov. 9, 2024, 12:07 p.m. UTC

From: Rob Bradford <[e-mail]>

The RISC-V unprivileged specification "31.3.11. State of Vector
Extension at Reset" has a note that recommends vtype.vill be set on
reset as part of ensuring that the vector extension have a consistent
state at reset.

This change now makes QEMU consistent with Spike which sets vtype.vill
on reset.

Signed-off-by: Rob Bradford <[e-mail]>
Reviewed-by: Daniel Henrique Barboza <[e-mail]>
Message-ID: <[e-mail]>
Signed-off-by: Alistair Francis <[e-mail]>
(cherry picked from commit f8c1f36a2e3dab4935e7c5690e578ac71765766b)
Signed-off-by: Michael Tokarev <[e-mail]>

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 776f377849..a9483ced92 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1006,6 +1006,7 @@  static void riscv_cpu_reset_hold(Object *obj)
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
+    env->vill = true;
 
 #ifndef CONFIG_USER_ONLY
     if (cpu->cfg.debug) {