diff mbox series

[v3,2/4] Skip NaN mode check for soft-float

Message ID 20241112164130.2396737-4-aleksandar.rakic@htecgroup.com (mailing list archive)
State New
Headers show
Series Improve Mips target | expand

Commit Message

Aleksandar Rakic Nov. 12, 2024, 4:41 p.m. UTC 
Skip NaN mode check for soft-float since NaN mode is irrelevant if an ELF
binary's FPU mode is soft-float, i.e. it doesn't utilize a FPU.

Cherry-picked 63492a56485f6b755fccf7ad623f7a189bfc79b6
from https://github.com/MIPS/gnutools-qemu

Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
---
 linux-user/mips/cpu_loop.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 462387a073..07c1ebe287 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -304,8 +304,10 @@  void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
     if (env->insn_flags & ISA_NANOMIPS32) {
         return;
     }
-    if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
-        ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
+    if (info->fp_abi != MIPS_ABI_FP_SOFT
+        && ((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
+           ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0))
+      {
         if ((env->active_fpu.fcr31_rw_bitmask &
               (1 << FCR31_NAN2008)) == 0) {
             fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");