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([193.104.68.137]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5cf03c8130dsm6137004a12.88.2024.11.12.08.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Nov 2024 08:42:30 -0800 (PST) From: Aleksandar Rakic X-Google-Original-From: Aleksandar Rakic To: qemu-devel@nongnu.org Cc: aleksandar.rakic@htecgroup.com, djordje.todorovic@htecgroup.com, cfu@mips.com, arikalo@gmail.com, peter.maydell@linaro.org, philmd@linaro.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, kwolf@redhat.com, hreitz@redhat.com, pbonzini@redhat.com, alex.bennee@linaro.org, pierrick.bouvier@linaro.org, berrange@redhat.com Subject: [PATCH v3 3/4] target/mips: Enable MSA ASE using a CLI flag Date: Tue, 12 Nov 2024 17:41:29 +0100 Message-Id: <20241112164130.2396737-5-aleksandar.rakic@htecgroup.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> References: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=rakicaleksandar1999@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 12 Nov 2024 12:37:38 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Enable MSA ASE using a CLI flag -cpu ,msa=on. Signed-off-by: Aleksandar Rakic --- target/mips/cpu.c | 16 ++++++++++++++++ target/mips/cpu.h | 1 + target/mips/internal.h | 2 +- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d0a43b6d5c..8e12d303de 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -494,8 +494,24 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) mcc->parent_realize(dev, errp); } +static bool mips_get_msa_on(Object *obj, Error **errp) +{ + MIPSCPU *cpu = MIPS_CPU(obj); + CPUMIPSState *env = &cpu->env; + return env->msa_on; +} + +static void mips_set_msa_on(Object *obj, bool value, Error **errp) +{ + MIPSCPU *cpu = MIPS_CPU(obj); + CPUMIPSState *env = &cpu->env; + env->msa_on = value; +} + static void mips_cpu_initfn(Object *obj) { + object_property_add_bool(obj, "msa", mips_get_msa_on, mips_set_msa_on); + object_property_set_bool(obj, "msa", false, NULL); MIPSCPU *cpu = MIPS_CPU(obj); CPUMIPSState *env = &cpu->env; MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index f6877ece8b..3e636535c6 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1191,6 +1191,7 @@ typedef struct CPUArchState { QEMUTimer *timer; /* Internal timer */ Clock *count_clock; /* CP0_Count clock */ target_ulong exception_base; /* ExceptionBase input to the core */ + bool msa_on; /* Enable MSA using a CLI flag -cpu ...,msa=on/off */ } CPUMIPSState; /** diff --git a/target/mips/internal.h b/target/mips/internal.h index 91c786cff8..bbe2acffe2 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -399,7 +399,7 @@ static inline void compute_hflags(CPUMIPSState *env) } } if (ase_msa_available(env)) { - if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { + if ((env->CP0_Config5 & (1 << CP0C5_MSAEn)) || (env->msa_on)) { env->hflags |= MIPS_HFLAG_MSA; } }