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Tsirkin" , Marcel Apfelbaum , =?utf-8?q?Herv=C3=A9_Poussin?= =?utf-8?q?eau?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Paolo Bonzini , Thomas Huth , qemu-arm@nongnu.org, Guenter Roeck , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PATCH 08/10] aspeed: Add uhci support for ast2400 and ast2500 Date: Tue, 12 Nov 2024 08:56:17 -0800 Message-ID: <20241112165618.217454-9-linux@roeck-us.net> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241112165618.217454-1-linux@roeck-us.net> References: <20241112165618.217454-1-linux@roeck-us.net> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=groeck7@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add UHCI support for ast2400 and ast2500 SoCs. With this patch, the UHCI port is successfully enabled on the ast2500-evb machine. Note that the EHCI controller on AST2400 and AST2500 does not support companion mode, so the UHCI controller is instantiated as stand-alone device and creates an additional USB bus. Reviewed-by: Cédric Le Goater Signed-off-by: Guenter Roeck --- Changes since RFC: - Rebased to v9.1.0-1673-g134b443512 - Added Reviewed-by: tag - Added explanation for not using EHCI companion mode hw/arm/aspeed_ast2400.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index ecc81ecc79..8a5d21459d 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -31,6 +31,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = { [ASPEED_DEV_FMC] = 0x1E620000, [ASPEED_DEV_SPI1] = 0x1E630000, [ASPEED_DEV_EHCI1] = 0x1E6A1000, + [ASPEED_DEV_UHCI] = 0x1E6B0000, [ASPEED_DEV_VIC] = 0x1E6C0000, [ASPEED_DEV_SDMC] = 0x1E6E0000, [ASPEED_DEV_SCU] = 0x1E6E2000, @@ -68,6 +69,7 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = { [ASPEED_DEV_SPI2] = 0x1E631000, [ASPEED_DEV_EHCI1] = 0x1E6A1000, [ASPEED_DEV_EHCI2] = 0x1E6A3000, + [ASPEED_DEV_UHCI] = 0x1E6B0000, [ASPEED_DEV_VIC] = 0x1E6C0000, [ASPEED_DEV_SDMC] = 0x1E6E0000, [ASPEED_DEV_SCU] = 0x1E6E2000, @@ -107,6 +109,7 @@ static const int aspeed_soc_ast2400_irqmap[] = { [ASPEED_DEV_FMC] = 19, [ASPEED_DEV_EHCI1] = 5, [ASPEED_DEV_EHCI2] = 13, + [ASPEED_DEV_UHCI] = 14, [ASPEED_DEV_SDMC] = 0, [ASPEED_DEV_SCU] = 21, [ASPEED_DEV_ADC] = 31, @@ -199,6 +202,8 @@ static void aspeed_ast2400_soc_init(Object *obj) TYPE_PLATFORM_EHCI); } + object_initialize_child(obj, "uhci", &s->uhci, TYPE_ASPEED_UHCI); + snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); object_initialize_child(obj, "sdmc", &s->sdmc, typename); object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), @@ -393,6 +398,15 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); } + /* UHCI */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uhci), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->uhci), 0, + sc->memmap[ASPEED_DEV_UHCI]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uhci), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_UHCI)); + /* SDMC - SDRAM Memory Controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { return;