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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7246a9bab70sm1417926b3a.152.2024.11.14.08.05.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:05:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 49/54] target/tricore: Convert to TCGCPUOps.tlb_fill_align Date: Thu, 14 Nov 2024 08:01:25 -0800 Message-ID: <20241114160131.48616-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/tricore/cpu.h | 7 ++++--- target/tricore/cpu.c | 2 +- target/tricore/helper.c | 19 ++++++++++++------- 3 files changed, 17 insertions(+), 11 deletions(-) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 220af69fc2..5f141ce8f3 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -268,8 +268,9 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU /* helpers.c */ -bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool tricore_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr); #endif /* TRICORE_CPU_H */ diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 1a26171590..29e0b5d129 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -173,7 +173,7 @@ static const TCGCPUOps tricore_tcg_ops = { .initialize = tricore_tcg_init, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, .restore_state_to_opc = tricore_restore_state_to_opc, - .tlb_fill = tricore_cpu_tlb_fill, + .tlb_fill_align = tricore_cpu_tlb_fill_align, .cpu_exec_interrupt = tricore_cpu_exec_interrupt, .cpu_exec_halt = tricore_cpu_has_work, }; diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7014255f77..8c6bf63298 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -64,16 +64,19 @@ static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address, { } -bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType rw, int mmu_idx, - bool probe, uintptr_t retaddr) +bool tricore_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr address, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr) { CPUTriCoreState *env = cpu_env(cs); hwaddr physical; int prot; int ret = 0; + int rw = access_type & 1; + + /* TODO: alignment faults not currently handled. */ - rw &= 1; ret = get_physical_address(env, &physical, &prot, address, rw, mmu_idx); @@ -82,9 +85,11 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, __func__, address, ret, physical, prot); if (ret == TLBRET_MATCH) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, - mmu_idx, TARGET_PAGE_SIZE); + memset(out, 0, sizeof(*out)); + out->phys_addr = physical; + out->prot = prot | PAGE_EXEC; + out->lg_page_size = TARGET_PAGE_BITS; + out->attrs = MEMTXATTRS_UNSPECIFIED; return true; } else { assert(ret < 0);