diff mbox series

[5/7,BCM2835,AUX,5/7] Suffix constants

Message ID 20241117225643.768322-5-ioan-cristian.cirstea@tutanota.com (mailing list archive)
State New
Headers show
Series [1/7,BCM2835,AUX,1/7] Replace hard-coded FIFO | expand

Commit Message

Ioan-Cristian CÎRSTEA Nov. 17, 2024, 10:56 p.m. UTC
The constants defined through the preprocessor must be unsigned. Also,
unsigned integer constants are consistent across different bases (see
section 6.4.4.1 of the C99 standard draft).

Signed-off-by: Ioan-Cristian CÎRSTEA <ioan-cristian.cirstea@tutanota.com>
---
 hw/char/bcm2835_aux.c | 52 +++++++++++++++++++++----------------------
 1 file changed, 26 insertions(+), 26 deletions(-)
diff mbox series

Patch

diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c
index 266d0dfdc7..e887076d9b 100644
--- a/hw/char/bcm2835_aux.c
+++ b/hw/char/bcm2835_aux.c
@@ -30,49 +30,49 @@ 
 #include "qemu/module.h"
 
 /* TODO: These constants need to be unsigned */
-#define AUX_IRQ         0x0
-#define AUX_ENABLES     0x4
-#define AUX_MU_IO_REG   0x40
-#define AUX_MU_IER_REG  0x44
-#define AUX_MU_IIR_REG  0x48
-#define AUX_MU_LCR_REG  0x4c
-#define AUX_MU_MCR_REG  0x50
-#define AUX_MU_LSR_REG  0x54
-#define AUX_MU_MSR_REG  0x58
-#define AUX_MU_SCRATCH  0x5c
-#define AUX_MU_CNTL_REG 0x60
-#define AUX_MU_STAT_REG 0x64
-#define AUX_MU_BAUD_REG 0x68
+#define AUX_IRQ         0x0U
+#define AUX_ENABLES     0x4U
+#define AUX_MU_IO_REG   0x40U
+#define AUX_MU_IER_REG  0x44U
+#define AUX_MU_IIR_REG  0x48U
+#define AUX_MU_LCR_REG  0x4cU
+#define AUX_MU_MCR_REG  0x50U
+#define AUX_MU_LSR_REG  0x54U
+#define AUX_MU_MSR_REG  0x58U
+#define AUX_MU_SCRATCH  0x5cU
+#define AUX_MU_CNTL_REG 0x60U
+#define AUX_MU_STAT_REG 0x64U
+#define AUX_MU_BAUD_REG 0x68U
 
 /* Register masks */
-#define MASK_AUX_MU_CNTL_REG 0x3
+#define MASK_AUX_MU_CNTL_REG 0x3U
 /* Mask for TX-related bits */
-#define MASK_AUX_MU_STAT_REG_TX 0xF00032A
+#define MASK_AUX_MU_STAT_REG_TX 0xF00032AU
 /*
  * Mask for RX-related bits.
  * XXX: It does not include receiver IDLE and receiver overrun for now.
  */
-#define MASK_AUX_MU_STAT_REG_RX 0xF0001
+#define MASK_AUX_MU_STAT_REG_RX 0xF0001U
 
 /* bits in IER register */
-#define IER_RX_IRQ_ENABLE  0x1
-#define IER_TX_IRQ_ENABLE  0x2
+#define IER_RX_IRQ_ENABLE  0x1U
+#define IER_TX_IRQ_ENABLE  0x2U
 
 /* bits in IIR register */
-#define IIR_IRQ_NOT_PEND 0x1
-#define IIR_TX_EMPTY 0x2
-#define IIR_RX_VALID 0x4
+#define IIR_IRQ_NOT_PEND 0x1U
+#define IIR_TX_EMPTY 0x2U
+#define IIR_RX_VALID 0x4U
 
 /* bits in CNTL register */
-#define CNTL_RX_ENABLE 0x1
-#define CNTL_TX_ENABLE 0x2
+#define CNTL_RX_ENABLE 0x1U
+#define CNTL_TX_ENABLE 0x2U
 
 /* bits in STAT register */
-#define STAT_TRANSMITTER_DONE 0x200
+#define STAT_TRANSMITTER_DONE 0x200U
 
 /* FIFOs length */
-#define BCM2835_AUX_RX_FIFO_LEN 8
-#define BCM2835_AUX_TX_FIFO_LEN 8
+#define BCM2835_AUX_RX_FIFO_LEN 8U
+#define BCM2835_AUX_TX_FIFO_LEN 8U
 
 #define log_guest_error(fmt, ...) \
     qemu_log_mask(LOG_GUEST_ERROR, \