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([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da2800absm136351505e9.25.2024.11.17.14.57.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Nov 2024 14:57:26 -0800 (PST) From: " =?utf-8?q?Ioan-Cristian_C=C3=8ERSTEA?= " X-Google-Original-From: =?utf-8?q?Ioan-Cristian_C=C3=8ERSTEA?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Ioan-Cristian_C=C3=8ERSTEA?= Subject: [PATCH 7/7] [BCM2835 AUX 7/7] STAT OVERRUN & IDLE Date: Mon, 18 Nov 2024 00:56:43 +0200 Message-Id: <20241117225643.768322-7-ioan-cristian.cirstea@tutanota.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241117225643.768322-1-ioan-cristian.cirstea@tutanota.com> References: <20241117225643.768322-1-ioan-cristian.cirstea@tutanota.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=jean.christian.cirstea@gmail.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUBJ_ALL_CAPS=0.5 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 17 Nov 2024 18:00:54 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This commit implements the required logic for receiver overrun and idle bitfields in the STAT register. Currently, the receiver is always reported as idle. Signed-off-by: Ioan-Cristian CÎRSTEA --- hw/char/bcm2835_aux.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c index 577d9a9be3..c9bce7d7d3 100644 --- a/hw/char/bcm2835_aux.c +++ b/hw/char/bcm2835_aux.c @@ -29,7 +29,6 @@ #include "qemu/log.h" #include "qemu/module.h" -/* TODO: These constants need to be unsigned */ #define AUX_IRQ 0x0U #define AUX_ENABLES 0x4U #define AUX_MU_IO_REG 0x40U @@ -50,11 +49,8 @@ /* Mask for TX-related bits */ #define MASK_AUX_MU_STAT_REG_TX 0xF00032AU -/* - * Mask for RX-related bits. - * XXX: It does not include receiver IDLE and receiver overrun for now. - */ -#define MASK_AUX_MU_STAT_REG_RX 0xF0001U +/* Mask for RX-related bits */ +#define MASK_AUX_MU_STAT_REG_RX 0xF0015U /* Mask for TX-related bits */ #define MASK_AUX_MU_LSR_REG_TX 0x60U @@ -70,6 +66,7 @@ /* bits in LSR register */ #define LSR_OVERRUN 0x2U +#define LSR_OVERRUN_OFFSET 0x1U /* bits in CNTL register */ #define CNTL_RX_ENABLE 0x1U @@ -77,6 +74,8 @@ /* bits in STAT register */ #define STAT_TRANSMITTER_DONE 0x200U +#define STAT_OVERRUN 0x10U +#define STAT_RECEIVER_IDLE 0x4U /* FIFOs length */ #define BCM2835_AUX_RX_FIFO_LEN 8U @@ -90,12 +89,12 @@ ##__VA_ARGS__ \ ) -static void bcm2835_aux_clear_overrun_bits(BCM2835AuxState *s) +static void bcm2835_aux_clear_overrun_bit(BCM2835AuxState *s) { s->lsr &= ~LSR_OVERRUN; } -static void bcm2835_aux_set_overrun_bits(BCM2835AuxState *s) +static void bcm2835_aux_set_overrun_bit(BCM2835AuxState *s) { s->lsr |= LSR_OVERRUN; } @@ -134,10 +133,17 @@ static void bcm2835_aux_rx_stat_update(BCM2835AuxState *s) { Fifo8 *rx_fifo = &s->rx_fifo; const bool rx_symbol_available = !fifo8_is_empty(rx_fifo); + const bool rx_overrun = (s->lsr & LSR_OVERRUN) >> LSR_OVERRUN_OFFSET; const uint32_t rx_fifo_level = fifo8_num_used(rx_fifo); s->stat &= ~MASK_AUX_MU_STAT_REG_RX; + /* + * Receiver overrun bit is set separately in bcm2835_aux_set_overrun_bit + * Receiver is always marked as idle. + */ s->stat |= (rx_fifo_level << 16) | + (rx_overrun << 4) | + STAT_RECEIVER_IDLE | (rx_symbol_available << 0); } @@ -340,7 +346,7 @@ static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size) case AUX_MU_LSR_REG: res = s->lsr; /* Overrun bit is self-clearing */ - bcm2835_aux_clear_overrun_bits(s); + bcm2835_aux_clear_overrun_bit(s); return res; case AUX_MU_MSR_REG: @@ -441,7 +447,7 @@ static int bcm2835_aux_can_receive(void *opaque) const bool is_rx_enabled = bcm2835_aux_is_rx_enabled(s); if (is_rx_fifo_full && is_rx_enabled) { - bcm2835_aux_set_overrun_bits(s); + bcm2835_aux_set_overrun_bit(s); } return !is_rx_fifo_full;