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Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 7/8] hw/riscv/virt: Set PCI_BUS_IO_ADDR0_ALLOWED flag on GPEX host bridge Date: Mon, 25 Nov 2024 15:05:34 +0100 Message-ID: <20241125140535.4526-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=philmd@linaro.org; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org See commit acead54c78 ("riscv: virt: Allow PCI address 0") all RISCV Virt machines set this flag. Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2feb851f15..4e1ce3a423 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1156,6 +1156,8 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, pio_base, NULL); object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, pio_size, NULL); + object_property_set_bool(OBJECT(dev), "allow-io-addr0-accesses", + true, &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -1803,7 +1805,6 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = TYPE_RISCV_CPU_BASE; mc->block_default_type = IF_VIRTIO; mc->no_cdrom = 1; - mc->pci_allow_0_address = true; mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;