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Tue, 26 Nov 2024 06:01:16 -0800 (PST) Received: from localhost.localdomain ([176.176.143.205]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-433b463abb4sm236443155e9.31.2024.11.26.06.01.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 26 Nov 2024 06:01:16 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Jiaxun Yang Subject: [PATCH v3 11/16] target/mips: Convert microMIPS LSA opcode to decodetree Date: Tue, 26 Nov 2024 14:59:57 +0100 Message-ID: <20241126140003.74871-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126140003.74871-1-philmd@linaro.org> References: <20241126140003.74871-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Simply call the generic gen_lsa(), using the plus_1() helper to add 1 to the shift amount. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241112172022.88348-6-philmd@linaro.org> --- target/mips/tcg/micromips32.decode | 8 ++++++++ target/mips/tcg/micromips_translate.c | 10 ++++++++++ target/mips/tcg/micromips_translate.c.inc | 5 ----- 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/target/mips/tcg/micromips32.decode b/target/mips/tcg/micromips32.decode index 333ab0969ca..0df9f0c59ff 100644 --- a/target/mips/tcg/micromips32.decode +++ b/target/mips/tcg/micromips32.decode @@ -9,3 +9,11 @@ # (Document Number: MD00582) # microMIPS64 Instruction Set # (Document Number: MD00594) + +&r rs rt rd sa + +%lsa_sa 9:2 !function=plus_1 + +@lsa ...... rt:5 rs:5 rd:5 .. ... ...... &r sa=%lsa_sa + +LSA 000000 ..... ..... ..... .. 000 001111 @lsa diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c index 49e90e7eca2..f0b5dbf655d 100644 --- a/target/mips/tcg/micromips_translate.c +++ b/target/mips/tcg/micromips_translate.c @@ -9,6 +9,16 @@ #include "qemu/osdep.h" #include "translate.h" +static inline int plus_1(DisasContext *ctx, int x) +{ + return x + 1; +} + /* Include the auto-generated decoders. */ #include "decode-micromips16.c.inc" #include "decode-micromips32.c.inc" + +static bool trans_LSA(DisasContext *ctx, arg_r *a) +{ + return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); +} diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 7a884222eed..73394554509 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -191,7 +191,6 @@ enum { /* The following can be distinguished by their lower 6 bits. */ BREAK32 = 0x07, INS = 0x0c, - LSA = 0x0f, ALIGN = 0x1f, EXT = 0x2c, POOL32AXF = 0x3c, @@ -1793,10 +1792,6 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) case INS: gen_bitops(ctx, OPC_INS, rt, rs, rr, rd); return; - case LSA: - check_insn(ctx, ISA_MIPS_R6); - gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) + 1); - break; case ALIGN: check_insn(ctx, ISA_MIPS_R6); gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2));