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Tue, 26 Nov 2024 06:01:24 -0800 (PST) Received: from localhost.localdomain ([176.176.143.205]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434a4d41fb4sm31646165e9.14.2024.11.26.06.01.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 26 Nov 2024 06:01:23 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v3 12/16] target/mips: Convert nanoMIPS LSA opcode to decodetree Date: Tue, 26 Nov 2024 14:59:58 +0100 Message-ID: <20241126140003.74871-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126140003.74871-1-philmd@linaro.org> References: <20241126140003.74871-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Simply call the generic gen_lsa() helper. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241112172022.88348-7-philmd@linaro.org> --- target/mips/tcg/nanomips32.decode | 6 ++++++ target/mips/tcg/nanomips_translate.c | 7 +++++++ target/mips/tcg/nanomips_translate.c.inc | 4 ---- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target/mips/tcg/nanomips32.decode b/target/mips/tcg/nanomips32.decode index 9cecf1e13d3..96d2299bfb0 100644 --- a/target/mips/tcg/nanomips32.decode +++ b/target/mips/tcg/nanomips32.decode @@ -6,3 +6,9 @@ # # Reference: nanoMIPS32 Instruction Set Technical Reference Manual # (Document Number: MD01247) + +&r rs rt rd sa + +@lsa ...... rt:5 rs:5 rd:5 sa:2 --- ... ... &r + +LSA 001000 ..... ..... ..... .. ... 001 111 @lsa diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c index 335a32845ed..3e77fcd23d3 100644 --- a/target/mips/tcg/nanomips_translate.c +++ b/target/mips/tcg/nanomips_translate.c @@ -13,3 +13,10 @@ #include "decode-nanomips16.c.inc" #include "decode-nanomips32.c.inc" #include "decode-nanomips48.c.inc" + +static bool trans_LSA(DisasContext *ctx, arg_r *a) +{ + gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); + + return true; +} diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 5d021f01128..0627f01c19e 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -399,7 +399,6 @@ enum { /* POOL32A7 instruction pool */ enum { NM_P_LSX = 0x00, - NM_LSA = 0x01, NM_EXTW = 0x03, NM_POOL32AXF = 0x07, }; @@ -3625,9 +3624,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) case NM_P_LSX: gen_p_lsx(ctx, rd, rs, rt); break; - case NM_LSA: - gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2)); - break; case NM_EXTW: gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5)); break;